Subject: Re: Is it ok to parallel logic gates?
Date: Fri, 6 Sep 2002 19:23:38 +0100
NNTP-Posting-Date: 6 Sep 2002 18:23:38 GMT
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unless your dealing with 100's of MHz it will be fine.
at high frequencies the propogation delay variance and difference in die to
device leg "track" length will cause nasty narrow glitches and collisons.
if your system does not "see" fast edges no probs.
Kijoma Solutions Ltd
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Stolen sig of the week:-
There are only 10 types of the people in the world
those who understand binary and those who don't
"Sir Charles W. Shults III" wrote in message
> Actually, this has been done. If the gates are on the same chip,
> really no issues that preclude doing it. Testing shows that their inputs
> have no effect on each other, and the outputs are usually so close in
> specification (such as propagation delay, switching time, output level and
> output current) that it will not matter if they are driven by the same
> conditions. However, if one gate fails, the other will "domino" with it
> is in contention for long enough.
> You best strategy is to use a separate buffer instead of putting gates
> parallel, if this is practical.
> Chip Shults
> My robotics, space and CGI web page - http://home.cfl.rr.com/aichip