Subject: Re: High impedance low noise
Date: Wed, 11 Sep 2002 19:25:47 +0100
NNTP-Posting-Date: Wed, 11 Sep 2002 18:27:20 +0000 (UTC)
X-Newsreader: Turnpike Integrated Version 5.01 U
In article <firstname.lastname@example.org>, fred bartoli
>Win Hill a écrit dans le message :
>> "fred wrote...
>> >Win Hill wrote...
>> >> Hi Jim. On Wednesday, September 4, 2002, you wrote:
>> >>> Win wrote,
>> >>>> In one opamp, yes, but that's not necessary a good approach. When
>> >>>> measuring voltage, the reason for considering an FET opamp operated
>> >>>> as unity-gain follower is to drive a second high-bandwidth low-Zin
>> >>>> amplifier stage that uses conventional components, such as current-
>> >>>> feedback opamps that have low noise compared to the FET, obviating
>> >>>> the need for the FET stage to have any gain. Well, a gain of 2x in
>> >>>> the FET stage would be nice, and has over 1MHz bandwidth with any of
>> >>>> the parts below. The follow-on G = 50 low-noise 1MHz stage is easy.
>> >>> Well, this was exactly my thinking too, but I keep hearing from others
>> >>> that "all (or most of) the gain should be in the first stage, for max
>> >>> sig/noise. We were pondering the trick of multiple fet op amp inputs
>> >>> all paralleled, then summed. I read somewhere that this is a trick for
>> >>> cancelling random noise. I think another engineer here tried that a
>> >>> while back and it did not work well. We are all having a meeting
>> >>> tomorrow, and I should know more then. I just don't have enough
>> >>> details yet.
>> >> Hi Jim, best wishes in your meeting. To explain the issue of one
>> >> vs. several stages. The situation is accurately understood by
>> >> the effect of each stage on the effective input noise. It's useful to
>> >> use input-noise-density squared, for a simple easy-to-understand
>> >> The formula below is for a three-stage amplifier. Please rewrite it
>> >> paper, to see it easier without the poor ASCII-character limitations.
>> >> v_n(in)^2 = v_n1^2 + (v_n2/G1)^2 + (v_n3/G1G2)^2
>> >> We can see that if the gain G1 of the 1st-stage in a 2-stage amplifier
>> >> is 1, and both stages have the same noise level v_n, the effective
>> >> noise will be v_n(in)^2 = v_n1^2 + v_n2^2 = 2 * v_n^2, which means
>> >> V_n(in) is sqrt 2 = 1.4 times the noise of the 1st stage alone.
>> >> where the common wisdom comes from, assuming that the 1st stage uses
>> >> lowest-noise amplifier, and saying that G1 = 1 is a bad thing.
>> >> However, we know that high-Z JFET amplifiers are much noisier than
>> >> low-Z wideband amplifiers. For example, an AD8011 has 2nV of noise,
>> >> compared to a JFET opamp with say 6nV of noise. Using the formula, we
>> >> see that the overall noise is sqrt(6^2 + 2^2) = sqrt 40 = 6.32nV.
>> >> is so close to 6nV we can ignore the extra noise from the 2nd stage.
>> >> If the 1st stage has a gain of 2x, the effect is more striking, 6nV vs
>> >> 6.08nV. Clearly the old rubric is wrong under these conditions.
>> >> . f_T e_n Cin max Vcc
>> >> . (MHz) (nV) (pF) (+/-V)
>> >> . ----- ----- ---- ------
>> >> AD743 4.5 2.9 18 18
>> >> LT1792 5.6 4.2 14 20
>> >> AD711 4 16 5.5 18
>> >> LT1057 5 13 4 20
>> >> OPA655 240 6 1.0 5.5
>> >> AD8011 * 2 low-Z 6.3 current-feedback, 57MHz at G = 10.
>> >> Thanks,
>> >> - Win
>> > Also don't forget the TI winners
>> > f_T e_n Cin max Vcc
>> > (MHz) (nV) (pF) (+/-V)
>> > ----- ----- ---- ------
>> > THS4021 350 1.5 1.5 +/-16 stable G>10
>> > THS4031 100 1.6 1.5 +/-16 stable G>2
>> > THS4011 290 7.5 1.2 +/-16
>> Indeed those are nice amplifers, but they aren't JFET input
>> oamps, and they have an input current of up to 6uA, which
>> would be a killer for Jim, I suspect!!
>I just found those amps for my VNA IF amplifier and their nice perfs made me
>forget this point.
>One not so nice point is that the lowest noise amps aren't unity gain
>stable, and that seems to be a constant, at least for the TI amplifiers.
>Do you have any idea about the reason(s) ?
>That's a too bad point for me because this prevent me from using them in the
>> - Win
>> - Win
I have an on-going minimum noise design task at 100kHz where the source
series cap is 0.7pF and a shunt cap following of 10pF.
Currently employing an LT1793 10MEGfeedback // with 6.8pF. The gbw of
this marginal for the design.
I have recently got the data sheet of the AD8065 145MHZ gbw 7nVroot Hz
and 0.6fA / root Hz employing Fastfet (jfet?)
Have requested samples so well see how it goes, in the past Ive had a
lot of work re-designing circuits to employ alternatives for AD opamps
that have been discontinued so there is my prejudice to overcome.
A new LT .9nVroot Hz op amp from linear has an application circuit
employing a Phillips Jfet front end.
Sure it works but the Jfet has no appropriate leakage or current noise
specifications in the data sheet.