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Reply-To: "fred bartoli"
From: "fred bartoli"
References: <firstname.lastname@example.org> <email@example.com>
Subject: Re: R & C tempco repeatability
Date: Fri, 13 Sep 2002 14:02:35 +0200
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NNTP-Posting-Date: 13 Sep 2002 14:00:54 MEST
Bill sloman a écrit dans le message :
> "fred bartoli" wrote in message
> > Bill sloman a écrit dans le message :
> > firstname.lastname@example.org...
> > >
> > > "fred bartoli" wrote in message
> > > news:email@example.com...
> > > > Still for my 100kHz IF amplifier for which I still want really
> > > > phase deviation.
> > As I don't want to go the high price way (glass caps...) and also don't
> > to control the temperature (to reach the target I'll need a 0.1°C
> > it seems the best way is a time multiplexed calibration. (maybe 1 point
> > of 100 or 200)
> > I did rejected this at first because I was afraid of cal signal leakages
> > the input refered noise floor is 0.15uV (6kHz BW), but sync demodulation
> > will easily lower this.
> > Now considering all the implications it seems I have no other choice and
> > after some thinking it may not be as difficult as I first thought.
> > This will also rise the point of the demodulators clocks leakages : can
> > put the IF amp and the demodulator on the same board ? A (huge :-) )
> > leakage on a 100R impedance from a 5V source at 100kHz is a 0.3fF
> > !!! All that not considering ground plane pollution.
> > And maybe I should want 10nV or 1nV to exploit all the possible dynamic
> > range of the detector.
> > Do you have some experience about this (demodulator and IF on the same
> > board) ?
> No. The closest I've got was variable gain amplifier with a gain of up to
> 10,000 at up to about 17MHz, where the DC operating point was stabilised
> slow negative feedback through a second variable gain path whose gain went
> down as the signal gain went up.
Fortunately, I have an alternance of gain stage(30db)/BPF(Q=10) that avoids
me the necessity of bias point stabilisation, and my frequency is 170 times
lower. But the overall gain will be 30+30+30+10+10+10 for a nice 120dB.
> The 80dB of gain was from the output of a a Burr-Brown OPA-655 sets up as
> transimpedance amplifier converting a the output current from a
> into a voltage, so it probably comes fairly close to your levels.
> With that little board I did spend time working out possible feed-back
> and blocking them - very nearly every amplifier chip on the system had a
> ferrite bead from its power rails to its decoupling capacitors, and most
> the decoupling networks included a nice lossy tantalum chip capacitor to
> kill any filter resonances. I didn't have to go to a second printed
> layout to kill any leakage paths (but I did have to add an one extra
> capacitor across the TI LTC2201 CMOS op amp, which had about 15pF of input
> capacitance which TI didn't specify on the data sheet).
This is mostly what I would have done too and is the right way to success.
> The job is definitely do-able - super-hetrodyne radios have been doing
> exactly this for many years.
Hmmm, not so sure the task is as easy as for radios :
1) radios never have signal generator locked on the frequency they receive
2) the signal they produce is AC and the DC part is absolutely out of
The useful signal for me is the DC part, and sync rectification of even the
slightest leakage can dramatically affect the expected accuracy.
For the RF signal, LO and PLL part I know I'll have to *perfectly* separate
the paths, by ( probably double) shielding each functionnal block. Just
think to the impact of a -100dB leakage on a weak -60 or -80db returned
I'm prepared to do a lot of plumbing.
> They did tend to have little metal boxes around
> the local oscillator, but those were mostly mounted onto single-sides
> printed circuit boards. If you lay out your circuit onto a four or six
> printed circuit board, with the inner layers largely devoted to solid
> and power planes, you can almost always skip the little metal shielding
Unfortunately this is a home project and I'm afraid that the cost of 4 or 6
layers will be prohibitive, so I'll probably have to shield the hard way. I
also know that I will have to solve the multilayer issue for the MCU board
but that's another story.
> You may need to put occasional slots in the buried planes to to keep
> clock return currents from flowing under sensitive bits of the front end,
> but there isn't any black magic involved.
I once design a fast high current power supply (150A transients in 100ns
left after the output bypass caps, with 10mV margin left to the PSU as the
regulation error band) and came OK with 2 GND planes : 1 for the GND power
and 1 as the precision analog ref. Even carefully studying the currents
flows and the layers order (12 layers available)... there was still some
weird inductive cross coupling between the 2 planes affecting the feedback
I finally solved this using FASTHENRY, a nice small prog easily findable on
the web, that models and show the current distribution of an arbitrary
shaped 2D structure of conductors vs frequency. I learned a lot on the
supposed "quality" of ground planes this way.
> Bill Sloman, Nijmegen
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