From: John Popelish
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Subject: Re: CMOS Propigation Delay
Date: Fri, 13 Sep 2002 18:26:15 GMT
NNTP-Posting-Date: Fri, 13 Sep 2002 14:26:15 EDT
Ron Watkins wrote:
> First off, im not a student, and this is not for a class. Sorry, but I
> get blasted like this all the time.
> Im an amateur hack trying to learn stuff.
> Say I had a CMOS logic gate who's output is connected to several other
> CMOS inputs. I have been told that the additional gates are not a
> driving problem as they are with TTL (where you can't typicaly connect
> more than 10 inputs to a single output). I have been told that with
> CMOS, as you add gates, it simply slows down the signal. I want to get
> some clarification on this topic.
> Are we taking the propigation delay between the input and output of
> the gate changing depending on how many other gates are hooked to it?
> If so, im assuming that in a low speed circuit, I could hook 20, 30,
> 40 etc... and just see a increase in the propigation delay for the
> gate? Is there a timing model which can give me a good idea of how
> much slowdown to expect for X gates?
The gate output has a spec on pull up and pull down current. Use the
pull up rating, because it is usually lower. Divide half of the
supply voltage by this current and you have an approximation of the
output resistance. Each gate also has ian input capacitance spec.
add up all the capacitances and figure the R*C time constant of that
output driving those inputs. This is a fair approximation of how fast
the gate can swing between states, in addition to the internal
propagation time for the gate itself (also in the spec sheet). Since
the output current goes up faster than the supply voltage does, while
the input capacitance increases only slightly as the supply voltage
goes up, running CMOS at a higher supply voltage speeds it up a bit.