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From: firstname.lastname@example.org (Tom Bruhns)
Subject: Re: How to Choose Cap to Filter Pwr for IC?
Date: 19 Sep 2002 14:07:01 -0700
NNTP-Posting-Date: 19 Sep 2002 21:07:01 GMT
email@example.com (Jeff Walther) wrote in message news:...
> I think I understand the basic principal of putting a small cap near the
> power Vcc pin of digital ICs so that the cap can supply extra current when
> the IC draws heavily. And it's my understanding that there's a tension
> between chosing a large or small capacitance in that large gives a greater
> reservoir of charge but small reacts to demand more quickly. Please
> correct me if my understanding is wrong or incomplete.
There's lots of info out on the web about this sort of thing. Have a
look, for example, at http://www.avxcorp.com/TechInfo_catlisting.asp
and the pages under that, especially the ones under the "ceramic"
link. Also, some IC mfgrs have some info on bypassing; I just
attended a Xilinx presentation on the topic, and the handout said it
was based on their XAPP623 ap note, which you should find on their web
In general, physically smaller caps with wider/more connections have
lower inductance, and it's inductance which limits the speed with
which they can respond (deliver whatever stored energy they have).
Also, using all the same value everywhere on the board is not
necessarily good because you can end up with parallel resonances
between the inductance of those caps and the capacitance of the power
planes on the board (or other such resonances); using an assortment of
values helps kill the resonances.
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