From: "Ryan Gammon"
Subject: xc9536 cpld & decoupling
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Sat, 28 Sep 2002 07:02:12 GMT
NNTP-Posting-Date: Sat, 28 Sep 2002 04:02:12 ADT
I have a xilinx xc9536 cpld that I'm trying to program. The programing
appears to work, and the device verifies correctly. Unfortunately, the
programmed chip doesn't seem to work properly.
Right now I have the inputs pulled high, and the outputs disconnected. The
outputs are outputting 3.8 V instead of 5 V, and three of the "inputs" are
somehow being pulled down to 1.6 V.
I've checked all the vcc's and gnd's and they're correct, so I'm guessing
that there must be something wrong with the programming.
I found a checklist at http://support.xilinx.co.jp/xapp/xapp104.pdf that
2. Provide both 0.1 uF and 0.01 uF capacitors at every VCC point of the
chip, attached directly to the nearest ground
I've got a 10 uF electrolytic cap in front of a regulator, and a bunch of
0.1 uf ceramics at all of my ic's, including the 3 Vcc's of the cpld. They
seem to be suggesting that I add extra 0.01 uf (ceramic?) cap's. This seems
redundant. I tried it anyway, but the device still didn't program correctly.
My questions are:
- Can a cpld verifiy correctly (as far as the programming software is
concerned), yet still give the weird behavior that I'm seeing?
- What's xilinx getting at re: using both 0.1 and 0.01 uf cap's for
Thanks for any help!