From: "Boris Nogoodnik"
Subject: Re: UART Design , HELPPPP
Organization: KGB, Ltd.
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Mon, 30 Sep 2002 05:31:48 -0400
NNTP-Posting-Date: Mon, 30 Sep 2002 05:31:48 EDT
"Paul Burke" wrote in message
> Starrie999 wrote:
> > HI all,
> > I am now in the process of designing an 8 bit uart for study purposes . In
> > some standard designs that I found in some university websites and other
> > free designs they have used a FIFO , and in some other designs they haven't
> > used a FIFO. They say since we are implementing it in an FPGA we dont need a
> > FIFO.
> > What is the logic behind this? Also why do we need a FIFO in a UART.
> > Thanks in advance.
> I've cut out all the crossposting. Take the UART logically, a bit at a
> time. Transmit is the easy bit. It's just a shift register, that loads
> with a start bit and the 7 or 8 bits of data when you write to it. If
> you have parity, you need to generate the parity (a tree of XORs) and
> load that too. The tail end is connected to stop bit level. After
> loading, you start a counter for the total number of bits you have to
> shift out, and let it count down to zero. Then you set the transmit
> ready bit. Job done.
> Receive is harder, because you don't know when a character is going to
> start, and your local clock will not be synchronised to (or even exactly
> the same frequency as) the sender's. So you look for a change of state
> on the receive line, and use that to set a counter (clocked at a
> multiple of the baud rate) which is used to sample the state of the
> input in the middle of the bits (that's the simplest version, there are
> other and better ways to do the job). The bits received are simply
> shifted into a register, and when you have enough you set the data ready
> flag. You check for overrun by the state of the stop bit received, and
> calculate parity if used in the same way as for transmit.
> As you can see, you don't need a FIFO, but the receiving system has to
> process each received character before the next one arrives, otherwise
> you miss it.
> Look at a data sheet for a simple UART, say the 6402.
> Paul Burke
Your answer is up to the point explanation of the basic UART implementation.
But modern high speed UART chips do use FIFO buffers to protect from possible
overrun/underrun conditions. I think it's where the confusion is. FIFO buffers
are just an added feature and not a part of the UART functionality and should
not be even considered in this context. It's just a next layer on top to
compensate for the possible timing problems caused by computer software. But
UART wasn't really designed for computers initially. It was just a converter
between the parallel code and single line serial transition media and back. And
actually early UARTs were designed as a replacement for mechanical
encoders/decoders used in teletypes, before the computers.