From: "Christopher R. Carlen"
Subject: Need advice wiring up a CPLD
Date: Wed, 02 Oct 2002 17:31:26 -0700
Organization: Sandia National Laboratories, Albuquerque, NM USA
NNTP-Posting-Date: Thu, 3 Oct 2002 00:30:26 +0000 (UTC)
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(Please skim down to "Question:" if you don't want to read the details...)
In our engine labs we have a "magic box" which is a chassis with a panel
covered with BNCs, connected to the inputs and outputs of a variety of
basic logic gates (AND, OR, etc). This magic box is used to implement
various glue logic functions for our research engine control,
experimental apparatus, and data acquisition control schemes.
There are two problems with the existing magic boxes: 1. They have
terrible crosstalk problems, since they were done with wire wrapping and
not much thought to the existance of such things as mutual inductance
and capacitance. 2. The scientists tend to use up a lot of one type of
gate, leaving the others unused. Then they come to me and say "I ran
out of AND gates" or "I need a 6-input OR gate, can you modify the magic
box?" They also come to me periodically asking for me to implement
various logical gizmos of somewhat greater complexity than the magic box
can handle, requiring the design of custom hardware.
Rather than get my name associated with the poorly functioning device
after performing mods, and rather than waste my time futzing with the
wiring of the thing to add more gates only to have to make another
hardware change in a few more months, I decided to get modern:
I plan to build a universal magic box with a Xilinx Coolrunner XPLA3
XCR3128XL-VQ100 CPLD device. This seemed like a good way to start
learning the ropes with PLDs, which I've been eager to do for some time.
My box will have nice ESD protection networks on each of an array of
32 BNC connectors. Each connector can be changed from a Schmitt trigger
input buffer, or to a 50R back terminated 3x paralleled 74ACTQ14 output
buffer, by switching a little DPDT switch (on the inside of the
chassis). A bi-color LED will go with each connector, and will glow red
for outputs active, and green for inputs active.
Most of the space on the new magic box PCB, which will fit directly into
the panel so I don't have to run any wires from the connectors to
anywhere, is consumed by the IO buffering, switches, and LEDs. So I
plan to fit the CPLD on a little daughterboard that will plug into the
main board, kind of like a giant DIP package. The CPLD daughterboard
will have available 40 IOs, the 4 global clock inputs, the JTAG signals,
and will have an on-board 3.3V regulator.
Everything is pretty well thought out so far, I think. The only problem
is, the CPLD has 84 IOs available, of which I plan to use up to 40. 32
IOs will be connected to the user BNCs for certain, and I will have a
little header on the main PCB for expansion to another 8 user IOs if
needed in the future, as well as a header for access to the global
clocks, which will also be jumper selectable to connect to four of the
BNCs, if desired.
Enough bells and whistles? ;-) I hope the CPLD will allow me to
reconfigure the logic available to the user on the fly, and even to
implement those "more complicated than just a few gates" functions that
get asked for now and then, without having to build a new physical
circuit prototype breadboard and PCB.
How should I map the user IOs to the CPLD IOs, ie. function blocks and
macrocells, so as to result in the greatest likelyhood of always being
able to route whatever functions I want, to the pins I choose?
There seem to be two possible approaches: 1. Take a few IOs from each
function block, so that all function blocks are ultimately represented
to the outside (example: take 5 random macrocells from each of the 8
function blocks, for 40 IOs). Or 2. Use all the macrocells of the
first few function blocks until my 40 IOs are mapped out, then leave the
rest of the function blocks available for internal-only routing
(example, take all 16 macrocells from the first 2 function blocks, plus
8 macrocells from the 3rd function block, leaving 5.5 function blocks
not connected to the outside).
Is this a wierd problem?
Thanks for comments!
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA