The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
Subject: Re: Altera FPGA as ISA I/O device
X-Newsreader: Microsoft Outlook Express 5.50.4522.1200
NNTP-Posting-Date: Fri, 04 Oct 2002 16:35:15 GMT
Organization: Insight Broadband
Date: Fri, 04 Oct 2002 16:35:15 GMT
Actually, this was what I was trying to say in my post. Sorry if it wasn't
You should not need additional reset circuitry for the FPGA. It
automatically resets after configuration.
"Steen Larsen" wrote in message
> Ru-Chin Tsai, just for completeness, you could also arrange to
> configure through the ISA interface. After booting the PC,
> automatically configuring the FPGA. You would probably need some
> added circuit to reset the FPGA (unless you were in a very controlled
> environment and could use a non-standard signal to reset the FPGA.)
> For what it is worth, you may want to look at my MS thesis design of
> master/slave parallel processing at www.tech-forge.com.
> Good luck,
> "cookielady" wrote in message
> > I was in charge of a design that was very similar to yours. You can
> > actually program the FPGA through the ISA bus. There are essentially
> > was to program the FPGA: JTAG (Byteblaster), EEPROM configuration
> > or the parallel method. This still will allow you to have upgradable
> > firmware without the need to re-program EEPROM devices and will get you
> > from under the issue of dual booting.
> > All of the information on how to do this is contained within the altera
> > documentation.
> > Keith
> > "Ru-Chin Tsai" wrote in message
> > news:firstname.lastname@example.org...
> > > I now emulate ISA bus model and my core design on the FLEX 10k. PC can
> > > communicate with my core design for large testbench. Now the FLEX 10k
> > > act as a I/O card device. It is assigned with a IRQ and a segment of
> > > I/O port address. ISA I/O device must be initialized at 'power on' of
> > > motherboard. And the OS will load my device driver when booting. The
> > > problem is that I use ByteBlaster(LPT) to download programming data of
> > > FPGA. So I must boot twice, one for programming FPGA as a ISA I/O
> > > device(contian ISA bus model and my core design) and the other for
> > > initialing ISA I/O device and loading my device driver. Does I can
> > > program FPGA without PC and ready the ISA I/O device first, then power
> > > on the PC? Which programming method sould I select?
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup