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From: "Ralph Wade Phillips"
Subject: Re: ISA IRQ signal active how long?
Date: Fri, 4 Oct 2002 11:44:52 -0500
Organization: Phillips Enterprises
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"Keith R. Williams" wrote in message
> In article <email@example.com>, mhsprang@NOcustomSPAMware.nl
> > "Ru-Chin Tsai" wrote in message
> > news:firstname.lastname@example.org...
> > > I design a ISA card with IRQ support. We know 8259's IRQ signal is
> > > active high. I have read many posts about ISA IRQ pin and remain
> > > feeling some confusions. Please help me solve these problems.
> > >
> > > 1. The ISA IRQ will be totem-pole or open-collector or tr-state output
> > > type.
> > > It seem to have no standard about this issue. Many answers were
> > > posted on
> > > newsgroup and I can't identify which one is correct output
> > > configuration?
> > You can use a normal totem-pole output.
> Not a good idea! You'll likely have dueling drivers. The correct way
> to drive ISA IRQs is open-collector or tristate (essentially OC).
You've not worked much with the ISA IRQ crap design, have you? It's
active HIGH. It's SUPPOSED to be totem-pole.
Yes, it's crap. It's worse than crap, it's what happens when you
feed crap to a horse - you get double-crap. But it IS. Sigh.
(Yes, the proper way to handle IRQs is active-low level-sensitive
with open-collector drivers. Not how IBM did it, however.)
> > > 2. When ISA card request interrupt. It must assert the IRQ signal. But
> > > how long
> > > does IRQ signal be asserted(active high)?
> > Until you service the interrupt. I have done it like this:
> > An interrupt is requested by setting a flip-flop (FF). The FF output is
> > connected to the ISA INTx signal. This FF is reset when the hardware is
> > accessed, by combining the output of the address selection logic and
> > or IOWR). So whenever my hardware is read from or written to, is clears
> > INT signal.
> A better solution is to leave the interrupt until the interrupting
> device no longer requires service.
But as soon as you touch the PIC in a PC, and clear it, if the IRQ
hasn't been cleared, it'll fire ANOTHER interrupt trap out there ...
> > > 3. Should I care the 8259 PIC act as edge-trigger or level-sensitive
> > > mode?
> > Level mode. That's standard in PC world.
> No it is not! The ISA bus is edge triggered. ...A real PITA, but
> never the less... PCI is negative level sensitive (a far better idea).
> This is why ISA interrupts cannot be shared, but PCI can.
And it's active HIGH, negating the usage of open collector designs.
Think about that - if you DO have two devices, they have to drive
the bus LOW to avoid firing an interrupt. So the first device interrupts on
OCs. If the SECOND device does NOT interrupt, then the line STAYS low ...
which is why it's totem pole. (I like open collector and disable the driver
when not interrupting myself ... but that's even risky in todays Plug/N/Pray
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