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NNTP-Posting-Date: Mon, 07 Oct 2002 22:39:57 CDT
From: "Dave VanHorn"
References: <firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org> <3DA184E7.B1F429F3@webaccess.net> <3DA22778.FD66989F@webaccess.net>
Subject: Re: Basic Stamp vs Pic processors
Date: Mon, 7 Oct 2002 22:40:17 -0500
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> I wasn't aware that that feature had gotten into standard products. I
> know there was interest when my group architected a chip with three AVR
> mega 103 cores in which one of them can modify all of the memory on the
> chip (there is no flash so I had to come up with a boot loader for
> initial testing of the chip). The mega 103 core has no instruction to
> write program memory so we made all of our memory dual port and the
> "master" AVR sees all of memory (data and program for all three AVRs)
> mapped into data space. We did not want the "master" AVR to be able to
> modify its program memory all of the time so you have to ground a pin on
> the chip to enable the "master" to write its own memory.
The 103 is obsoleted by the 128.
I'm routing boards now for a printer that uses two 128s, and a tiny 26. The
"master" and "slave" 128 re-write their code space themselves, and the
master also re-programs the T26 which is used as a battery charger, as
needed. I'm using an HC652 for inter-processor communication between the
128s, as their SPI ports are busy with other stuff.
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