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From: Ryan Gammon
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Subject: Bitscope schematics round 2
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Date: Tue, 08 Oct 2002 04:10:19 GMT
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There are a couple of things about the bitscope (see
http://www.bitscope.com/design) analog input buffer schematic at
http://www.bitscope.com/design/hardware/analog/ that I do not understand.
Q1: Notice how the dc-blocking capacitor is connected:
dc \ |
/ dc |
I worry about the capacitor in (1) doing something weird with parasitics
in the switch when it's in the dc position. If capacitors have thermal
noise, I suppose that's a bit of a worry too.
On the other hand, (2) disconnects the input from the output while
switching, whereas there is always a connection through the capacitor in
I know that when you use a relay, you're supposed to put a diode across
it to prevent it from blowing back due to an inductance-induced voltage
spike. Is the capacitor here performing a similar function?
Q2: The 1 Mohm resistor in parallel with the jfet input gives the
circuit its 1 Mohm input resistance. Leaving it out would give the
circuit an even higher input resistance. What would be the disadvantage
of leaving it out? I guess it acts somewhat like a pulldown resistor --
without it, a disconnected input would float. The probes for this scope
claim to be 10:1 10 Mohm/16 pF capacitance. Does the 10:1 attenuation
come from a voltage divider between 10 Mohm's in the probe and 1 Mohm's
in the scope?
Q3: C31 and R25 are used for input protection. It looks to me like R25
is a current limiter used when the input falls outside of the +/- 5V
range, and the 100pF cap is what AoE calls a "speedup cap". Right?
Q4: The output source follower looks a lot like figure 3.29 in AoE. Q6
is the source follower. Q3 looks like an emitter follower (lower output
impedance), though AoE ties the collector to +5 rather than to the
source of Q6. In AoE, Q7 sets up the current needed to make V_gs = 0,
and also provides temperature compensation. In the case of the bitscope,
I guess it would only provide temperature compensation, as Q3 and RV3
are not typically going to match.
RV3 sets the I_d operating point. Offset adjust is also set by RV3 --
when the drop across it matches Q3's V_be, the offset would be 0.
Capacitor C35 looks like a bypass capacitor designed to keep noise on
A+5V and A-5V from disrupting I_d.
Why is this called a vertical amplifier?
Thanks for reading!
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