The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
From: Chuck Simmons
Organization: You jest.
X-Mailer: Mozilla 4.61 [en] (X11; U; Linux 2.0.33 i586)
Subject: Re: Basic Stamp vs Pic processors
References: <firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org> <3DA184E7.B1F429F3@webaccess.net> <3DA22778.FD66989F@webaccess.net>
Date: Tue, 08 Oct 2002 04:42:30 GMT
NNTP-Posting-Date: Mon, 07 Oct 2002 21:42:30 PDT
Dave VanHorn wrote:
> > I wasn't aware that that feature had gotten into standard products. I
> > know there was interest when my group architected a chip with three AVR
> > mega 103 cores in which one of them can modify all of the memory on the
> > chip (there is no flash so I had to come up with a boot loader for
> > initial testing of the chip). The mega 103 core has no instruction to
> > write program memory so we made all of our memory dual port and the
> > "master" AVR sees all of memory (data and program for all three AVRs)
> > mapped into data space. We did not want the "master" AVR to be able to
> > modify its program memory all of the time so you have to ground a pin on
> > the chip to enable the "master" to write its own memory.
> The 103 is obsoleted by the 128.
> I'm routing boards now for a printer that uses two 128s, and a tiny 26. The
> "master" and "slave" 128 re-write their code space themselves, and the
> master also re-programs the T26 which is used as a battery charger, as
> needed. I'm using an HC652 for inter-processor communication between the
> 128s, as their SPI ports are busy with other stuff.
Interesting. I don't think we can change cores. Too much effort involved
since I know our on chip bus structure would have to change. That's
messy and I really don't want to go back to scratch debug again on this
chip. That took weeks the first time out. BTW, my "master" to "slave"
communication is quite easy given all of the dual port RAM.
The reason I have three AVRs is a performance issue. The AVR, even at
40MHz clock is too slow. Even three AVRs are too slow. To make three
work, we put in a special arithmetic unit that all three share. That put
2 of the AVRs at a constant 80% utilization and I think the master runs
around 50% - it is hard to measure because the load changes a lot.
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons email@example.com
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup