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From: "Technology Project Services"
Subject: ASIC Layout engineer - Scotland
Date: Tue, 8 Oct 2002 19:03:39 +0100
NNTP-Posting-Date: 8 Oct 2002 18:03:36 GMT
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
We are looking for a bright, highly skilled, ASIC Layout engineer to add to
the Design Team at our Design Centre. You will be implementing the company's
multi-GigaBit Interface Megacell technology in exciting new high-speed
As well as providing design services on internal design projects, you will
be part of a small team providing Technical Support to our Sales Team and to
customers throughout the world who will be incorporating this technology
into their own ASIC products.
We need you to have experience in laying out high speed, transistor-level
logic circuits (such as full-custom, mixed signal, and logic library cells)
for deep sub-micron ASICs using 0.18um process technologies, or smaller.
Clock rates or bandwidths of these designs will have been at multiples of
100MHz or even more than 1GHz.
We expect that you will have been laying out ASICs (and cells) such as these
for at least five years, and ideally for longer.
The company's tool suite is centred on Cadence tools, although tools from
other EDA vendors are also used.
It would also be advantageous for you to have experience in the use of
Verilog (or alternatively VHDL) for simulation and synthesis, and also with
HSPICE for transistor-level logic design.
This position is located just outside the Edinburgh City Bypass , You will
also spend time at the our company's design centre in Russia.
Interested give me a call
Technology Project Services (International) Limited
Tel: 0131 331 3030
Fax: 0131 331 2518
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