From: "Tom Faloon"
Subject: Re: Weird logic problem
Date: Thu, 10 Oct 2002 03:53:35 +0100
NNTP-Posting-Date: Thu, 10 Oct 2002 02:48:29 +0000 (UTC)
X-Newsreader: Microsoft Outlook Express 5.00.2615.200
Can you describe your address decoder circuit please?
If you are using just about any gate based decoder, be it your own design,
or perhaps something like a 74xx154 (4 to 16 line decoder), you can expect
narrow glitches on the outputs when the state of the address inputs change,
due to differences in propagation delays through the gates, or small timing
differences between the address lines. These glitches are often wide enough
and of sufficient amplitude to be seen as clock pulses by other devices.
These outputs should be 'cleaned up' by preventing them from switching
during address input transitions, and then enabling them when the addresses
are stable. e.g if you were using a 74xx154 to drive clock inputs, you
should hold G1 or G2 high while address bits are changing. This prevents all
inputs from glitching low. (Or simply hold G1 or G2 high, and strobe it,
with the address strobe, provided it does not straddle address transitions.)
I am not saying this is the cause of your problem, but it is consistent with
the behaviour you describe. i.e. The 74LVC373's always get latched when they
should, but also sometimes when they should not. These glitches (or runt
pulses) are likely to be very narrow, and probably not have a full logic
swing. It only takes a small load, or a small capacitance to kill some of
Take a look with a good digital storage scope, preferably using an active
probe. They are probably 1nS or less in width, but that is enough to latch a
lot of today's fast logic.
If you don't have a suitable scope, solder a small cap, (10pF to 100pF)
between signal and ground, near the 373 end. use SMT cap, or use a wire
ended with VERY short leads. See if this fixes it. (This is not a permanent
fix, just a means of investigating.)
Richard Webb wrote in message
> Hi all,
> I'm working on a high speed DSP board. From my DSP I've got some
> decoding which generates chip selects which allows me to write data to
> 74LVC373 latches. The problem is that the data is being latched at the
> times. I've found that when writing as intended the latches work fine, but
> the other latches which aren't being driven are seeing odd spikes on their
> enable lines, which latches data into them when it shouldn't be. The thing
> is that these weird spikes are stopped when I either put a scope probe on
> them, or when I touch my finger on that pin of the IC, or if i just touch
> the pin with a bare piece of wire. It's almost like the pin is
> despite being driven from another logic IC. Does anyone recognise this
> and know what might cause it? I can't find a mistake on the board, but I
> know there must be one becuase the prototype with the same circuit works
> great. Any help would be really appreciated, I'm pulling my hair out with
> this one!
> Richard Webb.