Subject: Re: C40x0 counter reset behavior?
Date: Sun, 13 Oct 2002 11:14:17 -0700
References: <0001HW.B9CEEFC70239EEC21662EAD0@news.covad.net> <firstname.lastname@example.org>
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On Sun, 13 Oct 2002 10:08:24 -0700, John Fields wrote
(in message <email@example.com>):
> On Sun, 13 Oct 2002 9:39:19 -0700, DaveC wrote:
>> The data sheets for the C4020/40/60 don't specify what happens to the
>> outputs when the RESET pin is brought low then high.
>> Do the pins simply all go low during reset, then begin counting once reset
>> is released? Or do they all go high for the reset period?
>> Can anyone enlighten me about this?
> My RCA CMOS databook shows all of the ripple stages being reset with
> all their outputs going low when RESET is pulled high. In addition,
> the clock input is disabled with RESET high, and on the 4060, the
> oscillator is also disabled. Pulling RESET low will enable the
> counters and allow their count outputs to follow the clock.
Is this a proper reset circuit for the CD40x0?
.1uF cap from vcc (12v) to reset; 1M resistor from reset to ground
I'm trying to reset the counter at power-on for just a few uS or mS. Not
really important how long reset is active. Even 1 S is fine.
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