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Subject: Re: A nice one-off project for a competent UK based FPGA designer :)
X-Newsreader: Microsoft Outlook Express 6.00.2600.0000
Date: Tue, 15 Oct 2002 01:43:00 GMT
NNTP-Posting-Date: Mon, 14 Oct 2002 21:43:00 EDT
Did you connect all 32 devices to the same clock? -Stan
"Peter" wrote in message
> In 1992 I designed a product which was a PC (ISA) card containing 32
> (yes thirty two) XC3064 devices. It is basically a complicated pulse
> generator. Each of the devices contains the same config data. There is
> also an XC3030 which implemented the PC interface and some other
> simple stuff.
> The FPGA config data, for all 33 devices, is loaded from a simple
> program running under MS-DOS which reads in a Motorola S-record file
> and loads it into the card.
> The customer had a few of these, then came back in 1996 for some more.
> By then, Xilinx had almost dropped these parts and I had to redesign
> the card to use a TQFP version of the 3064, of a higher speed than the
> original one. Fortunately it still worked!
> I say "fortunately" because there have always been config loading
> problems with Xilinx parts - if you had a lot of them on a board (I
> last did FPGA design in 1997). They were very sensitive to the CCLK
> edges, not too fast and not too slow. I had to play around with
> different types of CMOS drivers to get the edges exactly right, and I
> do have a 400MHz scope. There was no explanation for this behaviour,
> other than the CCLK input having multi-GHz-speed and picking up
> non-monotonic risetimes which a 400MHz scope did not show.
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