From: John Larkin
Subject: Re: My flyback experiment is on the web
Date: Tue, 15 Oct 2002 18:24:50 -0700
Organization: Posted via Supernews, http://www.supernews.com
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On Wed, 16 Oct 2002 00:07:58 GMT, John Popelish
>John Larkin wrote:
>> On Tue, 15 Oct 2002 19:12:16 GMT, John Popelish
>> >I disagree with you and Fred. The ringing should be a damped
>> >sinusoid, not a series of fractional sine pulses if it were just
>> It can't make a damped sine because of the fet substrate diode. This
>> waveform is characteristic of drain circuit ringing.
>I understand how the stray (inductor, wiring and drain) capacitance
>charged up to output voltage will drain through supply voltage and
>thus charge up the inductor with current which then drives the voltage
>below zero (assuming that output voltage is more than twice supply
>voltage). But that current is drained to zero through the diode, and
>then the capacitance is charged again towards supply voltage which
>runs the inductor current up the other way enough to drive the
>capacitance up to twice the supply voltage. But then all subsequent
>ringing should be centered on supply voltage, and not ever forward
>bias the diode. The rest of the wave should be a damped sinusoid
>centered around the supply voltage. This is not at all the waveform
>shown. I see signs of repeated turn on of the fet.
As I think about it, I'd be inclined to say you are right. But if you
look at the Vg-Vd waveform, the positive gate spikes nearly align in
time with the positive drain spikes. So during the 'low' parts of the
ringing phase, the gate is biased off, and during the high spikes the
gate is the most positive. This is backwards from what you'd get if
the gate was causing the drain spikes. It looks more to me like the
gate is being driven from the drain spikes through the D-G
capacitance. Besides, the gate spikes look too small to turn on the
So, where is the energy being stored during the 'low' periods? I've
seen this weird spiking before, and never really understood it.
Maybe the substrate diode is acting like a step-recovery diode, ie, a
high-value capacitance when foreward biased, storing charge for some
time after the current has turned around. The extended conductance
holds the inductor's low side down long enough for a fresh load of
current to be pushed into the inductor from the supply. This, if so,
would clearly be very bad for efficiency.
A test for this would be to plop a schottky diode in parallel with the
substrate diode, and see if the spikes go away, and maybe efficiency
Now that I think about it, I have seen this same waveshape in a
step-recovery-diode pulser simulation.
Cool, if true.