References: <7FVr9.170534$S32.email@example.com> <7yWr9.170725$S32.firstname.lastname@example.org>
Subject: Re: Aylward, Engelhardt: Noise in a transient sim?
X-Newsreader: Microsoft Outlook Express 5.50.4807.1700
Date: Fri, 18 Oct 2002 17:49:05 GMT
NNTP-Posting-Date: Fri, 18 Oct 2002 13:49:05 EDT
Organization: Cox Communications
"Kevin Aylward" wrote in message
> "Mike" wrote in message
> > "Kevin Aylward" wrote in message
> > news:NVVr9.email@example.com...
> > > I think I see what your getting at. You mean effectively having the
> > > noise of a device that is usually only given in the frequency
> domain, be
> > > given in the time domain. This would seem to be a bit tricky, and
> > > probably more involved then what one really requires. i.e. I can't
> > > bothered with all that effort:-)
> > That is what I mean, and yes, it is what I require...
> > > The deal is though, you can get a pretty good estimate by worst
> > > and erroring on the high side. I have simulated, e.g. VCO's and
> > > put various signals on the power supply to see the effect. Its often
> > > case that it is extraneous noise that is the issue with high
> > > designs, such that the normal circuit noise is not that relevant. If
> > > have digital switching in analogue circuits, it difficult to predict
> > > just what noise is going to be anyway.
> > I can isolate my circuits from supply and digital noise well enough
> that the
> > dominant contributors to my VCO jitter are the FET noise sources.
> Famous last words:-)
> You know, I rarely find this to be the case. You must have a pretty
> digital noise free environment. I assume this is jfets, rather then
> 2.5GHz cmos i.c. vco's. Getting, say 80+dbs supply rejection from DC to
> 5Ghz is some feat in an ic.
CMOS, any frequency from 250MHz to 2.5GHz. Digital is anywhere from 10k
gates to >1M gates. The VCO is part of a PLL, typically in a clock recovery
system. I don't need the rejection you think I do.
> > There are various estimation methods that yield reasonably accurate
> > jitter estimates from AC simulations; Hajimiri's Impulse Sensitivity
> > Function is the one I see used most often. It works well, but to
> achieve the
> > best accuracy, you have to run separate simulations at different bias
> > over a cycle to find the noise at each bias point, in addition to all
> > transient simulations required to construct the sensitivity function.
> > significantly easier, and usually faster, to run a transient noise
> > simulation and extract the noise from that.
> I do have one or two papers on this sort of stuff... Always thought it
> was a bit of an overkill. In addition, none of them seem to agree with
> each other. I take a more engineering approach. Estimate the maximum
> noise, multiply it by pi, and see if looks ok. In real life, the
> performance is always worse then what you think. I have recently spent a
> bit of time in getting large rejections in VCOs and their bias circuits.
In real life, my actual results are within 10% of the theoretical jitter,
and I'm assuming that power supply noise and digital switching noise are
zero. They aren't, of course, but even in high performance applications,
they aren't significant contributors (in my circuits).
-- Mike --