Reply-To: "Kevin Aylward"
From: "Kevin Aylward"
References: <7FVr9.170534$S32.firstname.lastname@example.org> <7yWr9.170725$S32.email@example.com>
Subject: Re: Aylward, Engelhardt: Noise in a transient sim?
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Fri, 18 Oct 2002 21:48:32 +0100
NNTP-Posting-Date: Fri, 18 Oct 2002 21:48:32 BST
"Mike" wrote in message
> "Kevin Aylward" wrote in message
> > >
> > > I can isolate my circuits from supply and digital noise well
> > that the
> > > dominant contributors to my VCO jitter are the FET noise sources.
> > >
> > Famous last words:-)
> > You know, I rarely find this to be the case. You must have a pretty
> > digital noise free environment. I assume this is jfets, rather then
> > 2.5GHz cmos i.c. vco's. Getting, say 80+dbs supply rejection from DC
> > 5Ghz is some feat in an ic.
> CMOS, any frequency from 250MHz to 2.5GHz. Digital is anywhere from
> gates to >1M gates. The VCO is part of a PLL, typically in a clock
> system. I don't need the rejection you think I do.
> > > There are various estimation methods that yield reasonably
> > VCO
> > > jitter estimates from AC simulations; Hajimiri's Impulse
> > > Function is the one I see used most often. It works well, but to
> > achieve the
> > > best accuracy, you have to run separate simulations at different
> > points
> > > over a cycle to find the noise at each bias point, in addition to
> > the
> > > transient simulations required to construct the sensitivity
> > It's
> > > significantly easier, and usually faster, to run a transient noise
> > > simulation and extract the noise from that.
> > I do have one or two papers on this sort of stuff... Always thought
> > was a bit of an overkill. In addition, none of them seem to agree
> > each other. I take a more engineering approach. Estimate the maximum
> > noise, multiply it by pi, and see if looks ok. In real life, the
> > performance is always worse then what you think. I have recently
> > bit of time in getting large rejections in VCOs and their bias
> In real life, my actual results are within 10% of the theoretical
Ahmmm...Don't take this the wrong way, but I find this had to accept.
Its difficult enough doing this for normal circuit characteristics in
spice, let along for noise. Transistors, for starters are simple not
characterised very accurately for noise. 1/f could be all over the
For example, I have one paper by Rick Poore, Agilent EEsoft EDA
(whatever that means) that states for 1/f noise, there are no closed
form expressions. I have other papers which go into amazing mathematical
detail, so I am certainly dubious of a 10% accuracy claim.
> and I'm assuming that power supply noise and digital switching noise
> zero. They aren't, of course, but even in high performance
> they aren't significant contributors (in my circuits).
Again, you must be dealing with quite limited noise performance then.
For example, in medical ultrasound effective input noise might be 0.1
nv/sqrthz. Getting rid of hf clocking noise is almost impossible in
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.