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From: Chuck Simmons
Organization: You jest.
X-Mailer: Mozilla 4.61 [en] (X11; U; Linux 2.0.33 i586)
Subject: Re: DSP 2's complement vs straight binary
References: <3DAFA892.50B1E677@webaccess.net> <firstname.lastname@example.org>
Date: Sat, 19 Oct 2002 05:24:02 GMT
NNTP-Posting-Date: Fri, 18 Oct 2002 22:24:02 PDT
> Chuck Simmons email@example.com
> >StevJensen wrote:
> >> This does generate a question though.
> >> Is there some particular advantage in using this common mode/zero method
> >> or is it just convenient in some situations.
> >No. The last chip design architecture I worked on I hammered away on
> >getting inverters. They are cheap! Just about a square micron or less.
> >No effect on competative edge, after all. They argued with me until I
> >submitted and ate the extra instruction. The adavantage, if any, is that
> >the SAR in the ADC is binary. I don't mind. I just want a little
> >inverter. I will surely go through that exercise again another day.
> I must be missing something here. I am trying to see why you want to
> do this (and failing miserably). On one hand you are complaining
> about the added XOR instruction, but the implication is that you are
> using signed math instructions. There is a lot of overhead with signed
> math. Either the compiler must generate more code to handle it or if your
> uP does have signed op codes then more clock cycles are consumed
> by the internal microcode. Also unless you bias the input to the
> ADC so that it outputs hex80 (8bit) with a null signal it seems unlikely
> that you would actually obtain the results you wanted. All the ADCs I
> am familiar with ran a 2R ladder divider from 0v to vRef until the comparator
> flipped. Are you talking about using something that is a single chip
> Amp/Sample&Hold/ADC with dual conversion? I think these gave output
> like you are talking about, but I never actually used one.
Errrr. What is the time penalty for signed arithmetic? What extra code?
The processor does most instructions including the entire arithmetic set
in one clock cycle. One thing I asked for in the architecture was a
17X17 multiplier accumulator with a 40 bit accumulator that operates in
one clock whether used signed or unsigned. Signed arithmetic is no
problem by design. They just happened to have the article I wanted at
another design center.
I have a single A/D converter and a six channel mux with sample and
holds on the chip with the processors. One stop shopping if you will.
The full scale range is 2 volts centered on a common mode of 1.2 volts.
Don't ask. That's what they had to give me in mixed signal.
> >To think. 25 years ago, Burr-Brown had some conversion products with an
> >XOR built in so you could choose. We seem to have gone backward from
> >Yes. I created the table because the MSB inversion is not really
> >intuitive as we have seen.
> True enough.
I have another curious shortcut that I have been criticized for. If I
have to do a multiple precision negation of a 2's complement A/D result,
I use 1's complement because it is faster and the error is in the noise.
I have to argue that one from time to time. I don't frivol away
instruction cycles. I'm not a good typist so I really like to avoid
instructions in order to stave off carpal tunnel syndrome.
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons firstname.lastname@example.org
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