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Subject: Re: Aylward, Engelhardt: Noise in a transient sim?
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Date: Sat, 19 Oct 2002 06:49:05 GMT
NNTP-Posting-Date: Sat, 19 Oct 2002 02:49:05 EDT
Organization: Cox Communications
"Kevin Aylward" wrote in message
> "Mike" wrote in message
> > In real life, my actual results are within 10% of the theoretical
> Ahmmm...Don't take this the wrong way, but I find this had to accept.
> Its difficult enough doing this for normal circuit characteristics in
> spice, let along for noise. Transistors, for starters are simple not
> characterised very accurately for noise. 1/f could be all over the
> For example, I have one paper by Rick Poore, Agilent EEsoft EDA
> (whatever that means) that states for 1/f noise, there are no closed
> form expressions. I have other papers which go into amazing mathematical
> detail, so I am certainly dubious of a 10% accuracy claim.
Rick's a pretty sharp guy. I don't have his paper here at home, but IIRC,
he's saying that there's no closed form solution to calculate the noise
accumulation of an open loop VCO. That's correct, if you assume that 1/f
noise has no low frequency corner. In fact, though, it does have a low
frequency corner, and that prevents the integrated 1/f noise power from
diverging. There's still no _convenient_ closed form solution due to the
complexity of the integrand, but a little mathematical acuity produces an
accurate, short closed-form solution. I seem to recall that one of Poore's
reference came up with a closed form solution, but the complexity of the
solution was almost as bad as the original problem. That's open loop,
though, and we don't use our VCOs open loop.
Once the VCO is placed in a PLL, a closed form solution is easily obtained.
McNeill finds the jitter of a PLL in his thesis, and presents the results in
his JSSC paper (1997, IIRC). The extension of McNeill's results to flicker
noise are straightforward.
That's not to say that open loop calculations aren't valuable. They are, in
particular because open loop results can be related to closed loop results.
It's easy to do for white noise (see McNeill's thesis and paper), but much
more difficult to do for flicker noise. That relationship is key, since an
open loop simulation is typically orders of magnitude shorter than a closed
loop PLL simulation - especially with noise.
I'm currently using one of the standard foundry CMOS processes, for which
there has been a fair amount of noise characterization done. Our experience
is that the noise models are quite accurate. It sure surprised me.
As for your dubiousness, you're not alone. I'm not detailing everything I
do, but I built my first PLL more than 15 years ago, and it had lots of
noise problems. I've probably worked on 10 of them since then, and with each
one, learned more about the sources and cures of noise problems. The steps
we follow and precautions we take are based on years of experience. Each
time we overcame a problem, we unmasked the next one, and tried to figure
out what to do about it. In the past couple of years, our jitter has been
dominated, as near as we can tell, by the device noise.
> > and I'm assuming that power supply noise and digital switching noise
> > zero. They aren't, of course, but even in high performance
> > they aren't significant contributors (in my circuits).
> Again, you must be dealing with quite limited noise performance then.
> For example, in medical ultrasound effective input noise might be 0.1
> nv/sqrthz. Getting rid of hf clocking noise is almost impossible in
> tyhese situations.
Not limited, just different. The equivalent thermal noise voltage at the
input of a reasonably good 2.5GHz VCO is around 1.5nV/sqrtHz. In a 0.18u
process with small devices, the 1/f - thermal noise intercept might be as
high as 100MHz. The primary contributor to jitter is low frequency flicker
-- Mike --