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Subject: Re: Aylward, Engelhardt: Noise in a transient sim?
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Date: Sat, 19 Oct 2002 16:53:14 GMT
NNTP-Posting-Date: Sat, 19 Oct 2002 12:53:14 EDT
Organization: Cox Communications
"Mike Monett" wrote in message
> Mike wrote:
> > In real life, my actual results are within 10% of the theoretical
> > and I'm assuming that power supply noise and digital switching noise are
> > zero. They aren't, of course, but even in high performance applications,
> > they aren't significant contributors (in my circuits).
> > -- Mike --
> Mike, how do you do that? Please tell us more. Crosstalk in high frequency
> pll's is extremely difficult to model.
> Are you talking about measured results compared to simulations?
> If so, given the non-ideal performance of bypass caps, the noise induced
> bond wire inductance, the skin effect and prop delay of the ground plane,
> the problem of probing and measuring the results, how do you include these
> effects in your simulation?
> If you have some magic layout tricks that overcome these problems, please
> us your secrets.
You want _my_ secrets? In a thread a couple months ago, you wrote, "I'm down
to measuring less than 1uV in a 7GHz bandwidth, and things are starting to
get difficult." However good my performance is, you're doing far, far
Here's the measured jitter performance of the Silicon Labs Si5020, at
They get 1.5ps RMS jitter, which is in line with my results. Broadcom
reports 1ps RMS ; their paper also describes how they modeled noise in
the PLL. The level of performance reported by Broadcom and SiLabs is only
practically possible when there are no significant external interference
 Momtaz, et al, "A Fully Integrated SONET OC-48 Transceiver in Standard
CMOS," IEEE Journal of Solid State Circuits, vol 36, no 12, December, 2001.
-- Mike --