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From: Chuck Simmons
Organization: You jest.
X-Mailer: Mozilla 4.61 [en] (X11; U; Linux 2.0.33 i586)
Subject: Re: DSP 2's complement vs straight binary
References: <3DB0EC8B.4C91F189@webaccess.net> <firstname.lastname@example.org>
Date: Sun, 20 Oct 2002 15:49:44 GMT
NNTP-Posting-Date: Sun, 20 Oct 2002 08:49:44 PDT
> Chuck Simmons email@example.com
> >Errrr. What is the time penalty for signed arithmetic? What extra code?
> >The processor does most instructions including the entire arithmetic set
> >in one clock cycle. One thing I asked for in the architecture was a
> >17X17 multiplier accumulator with a 40 bit accumulator that operates in
> >one clock whether used signed or unsigned. Signed arithmetic is no
> >problem by design. They just happened to have the article I wanted at
> >another design center.
> If you have been using custom architecture that can do single clock math
> then that explains a lot.
When you do an ASIC, you get to shop for bits and pieces. However, my
prcessors are AVRs. All of the arithmetic instruction set is one clock
cycle in standard AVRs. If I recall, the AVRs with an 8X8 multiply do
the multiply in one clock cycle
> >I have a single A/D converter and a six channel mux with sample and
> >holds on the chip with the processors. One stop shopping if you will.
> >The full scale range is 2 volts centered on a common mode of 1.2 volts.
> >Don't ask. That's what they had to give me in mixed signal.
> "Flash" comparator or do they still use the internal clock/scan arrangement?
Flash is pretty nasty about area. I needed 1 usec or less for 10 bit
conversion. The part, in the end, has 0.6 usec conversion time. The A/D
is a SAR type and completes a 10 bit conversion in 12 clock cycles. It
can be optionally short cycled.
> >> >Yes. I created the table because the MSB inversion is not really
> >> >intuitive as we have seen.
> >> True enough.
> >I have another curious shortcut that I have been criticized for. If I
> >have to do a multiple precision negation of a 2's complement A/D result,
> >I use 1's complement because it is faster and the error is in the noise.
> >I have to argue that one from time to time. I don't frivol away
> >instruction cycles. I'm not a good typist so I really like to avoid
> >instructions in order to stave off carpal tunnel syndrome.
> Hardly criticism, you appear to know what you are talking about. I am
> just trying to update my knowledge somewhat.
> Not sure about this 1's complement thing. I would have to see it written
> out to make sure that I had any idea of what you are referring to.
> I do know that is very easy to compute a result where it is utterly absurd
> (actually counterproductive being in effect an additional noise source)
> to assume that the low order bits have any meaning at all.
> Some people just do not get this, so I can see your problem here.
To negate a 2's complement number, you bitwise complement it and add 1.
I don't bother to add 1. That saves a cycle but introduces a 1 LSB
Actually, the LSBs are somewhat useful in a noisy environment. They tend
to average to the correct result as long as the noise is uncorrelated.
In designing IIR filters and integrators, this is useful to know about.
Even though I cascade second order filters to avoid extreme coefficient
sensitivity and roundoff problems in fixed point implementation, I still
get some benefit from noise. This is particularly true in closed loop
systems where noise prevents limit cycling around zero.
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons firstname.lastname@example.org
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