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From: Paul Burke
Subject: Re: PCB routing
Date: Fri, 25 Oct 2002 07:47:14 +0000
Organization: Scazon Systems
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Alex C wrote:
> How do we determine thickness of line width to route when dealing with power
> or signal traces on a PCB? Does the location ( either surface layer or
> sandwitch in between dielectric) changes the properties of the thickness of
> the trace?
> normally what is the size of a min via drill to use for power or signal? and
> also what is the clearance to use for these via if it's surrounded by a
Generally power signals should be as big as the spare space on the PCB
will allow. Connect them by LOTS of vias if they change layer, and make
these vias quite big. If it's IC power you are talking about, get the
VCC tracks into a nice distribution pattern, and the ground well
For signals, the line width is governed mostly (at least at lower
frequencies) by a combination of what your PCB manufacturer can do
(don't forget that the finished line width is rather less than the width
you lay down, due to the etching process) and convenience- it's easier
to break narrow tracks than wide ones. So you end up balancing packing
density against manufacturability.
Don't forget to route critical paths first.
Clearance is usually another compromise. You want wide clearance so you
don't accidentally bridghe the gap, and for ground=- connected holes, so
you don't need a 1000W iron to make the solder flow. But you want small
clearance to get the flood fill into the parts other copper can't
I try to stick to 8 thou tracks, 0.5mm vias minimum, the manufactureres
seem comfortable with this.
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