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Subject: Re: Bypass capacitor position
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
Date: Fri, 25 Oct 2002 11:07:50 GMT
NNTP-Posting-Date: Fri, 25 Oct 2002 13:07:50 MET DST
"Richard Haendel" schrieb im Newsbeitrag
> Everyone knows that bypass capacitors should be as close as possible to an
> ic's power and ground leads. That's easy, of course, in the case of some
> PICS (for example) when power and ground are directly opposite to each
> and your using an ic socket that has room for a small capacitor.
> But my question is: can the capacitor be as far away as, say, .2" or .4"
> still be effective (at about 8Mhz)? If the cap can't be equi-distance from
> both leads, should it be closer to positive or ground? Or does it really
> Note that I'm talking about pc boards with through hole devices, not
> breadboads and not smts.
> Richard Haendel
this is a good question, as it shows the dilemma today's digital designers
are in. Because it is one point analogue understanding is needed to design
even with digital circuits.
To evaluate the bypass or decoupling capacitor, you first need to understand
its function. This goes down to discrete parts.
Inside the digital IC there are for example totem-pole output stages, where
a P-Fet and an N-Fet can short the output to either supply or make it high
Now when they change state, the charge contained in the capacities of the
outputs (traces and input capacitance of next stages) and internal gate
capacitances has to be ditched into the gnd and sucked from the supply.
Moreover all the stages change in the same moment at rising or falling clock
edge, independent of the clock frequency. So it depends more on the
technology (or maximal clock frequency). Even at a low clock frequency a
fast device will change state in the same short time and creates current
spikes of the same height as with high toggle frequencies.
Certainly the capacitance of output and clock lines dominates, so a small
47-100 ohms resistor directly at the output pin in series with the load
decouples the load capacity and reduces the peak current flow.
Also the reduction of output lines and setting unused outputs in high
impedance will help.
Now when a current surge is sucked in from the positive supply, the same
current flows into the ground. If there are no capacitors, the current has
to flow all the way from/into the power supply.
All resistance and inductivity of these two lines will cause a voltage drop,
the positive voltage gets less and the gnd voltage jumps up(gnd bounce)
compared to the power supply. So the voltage across the chip gets reduced
and when many lines change, it might not function any more without errors.
The output voltages can leave the specified range and trigger the input of a
following chip erroneously. This is especially the case with TTL logic,
because the maximum ground low level should be kept within a few hundred mV,
whereas the positive supply can bounce more.
The capacitor supplies this current for the short moment and maintains the
That is also the reason for making a gnd plane with very low resistance.
With modern Cmos devices a +supply plane and a gnd plane have become equally
important, because the switchover point is in the middle of the supply
So if you wire up fast chips on a breadboard, the caps are absolutely needed
and should be as near as possible, whereas a four or more layer board with
gnd and Vcc planes might not need any caps at all for proper functioning.
electronic hardware designer
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