From: "Tom Faloon"
Subject: Re: Bypass capacitor position
Date: Fri, 25 Oct 2002 14:58:13 +0100
NNTP-Posting-Date: Fri, 25 Oct 2002 13:57:13 +0000 (UTC)
X-Newsreader: Microsoft Outlook Express 5.00.2615.200
It is important that there is a low impedance path between the capacitor,
and the pins it is decoupling. This is more important than the physical
distance. To achieve this, always keep the inductance low by making the
tracks as thick and short as reasonably possible, and try to avoid vias. The
final solution is always a 'best compromise'
Assuming you have a simple, double sided board, without a 'ground layer', do
as above and you will not have a problem at 8 MHz, even if the total track
length is 0.4" Just keep the tracks reasonably thick. (Say about .040" or
0.050" or more.) Via inductance won't be significant, and you can avoid vias
anyway, since you are using through hole components.
Note: Frequency is not the only issue here, rise time is important too. If
you are using a fast device, with fast rise times, then decoupling is more
critical, even if it is run at a low frequency. I assume that is not so in
Re your question on cap position.
If the cap can't be equi-distance from both leads, it doesn't really matter
which one it is closest to:
BUT if you have a copper layer dedicated as a ground plane, then put the cap
close to the supply pin, and take the other end of the cap directly to
ground, to minimise impedance. (The ground plane will give a nice low
impedance path back to the 0 V pin.)
The ideal is to have dedicated ground and power planes, with NO tracks on
them, only vias. This keeps power and decoupling path impedance to a
minimum. Of course this is a luxury which we can't always afford, but it
becomes more important with hi speed logic !
Datacomm Uk Ltd. Cambridge