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From: "Harry Dellamano"
Subject: Re: Flyback ringing examined further
Date: Fri, 25 Oct 2002 14:44:52 -0700
Organization: Posted via Supernews, http://www.supernews.com
References: <3DB0CAF1.5010904@BOGUS.earthlink.net> <3DB223BD.9070403@BOGUS.earthlink.net>
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"Chris Carlen" wrote in message
> CDT wrote:
> > If ringing is inevitable why not add some additional
> > capacitance (as is done in TV flyback circuits) to
> > make the ringing period something like 2X the gate
> > drive frequency. This will be a "tuned" flyback but
> > at least you could put the "ringing" in a place where its
> > useful. This should stop the squiggles since you will turn
> > the FET on at precisely the correct time that the squiggle
> > tries to go postive for the 1st time.
> Yeah, but what will happen when the load changes and the PWM controller
> changes the duty cycle? I think that for a constant load condition,
> with constant duty cycle drive, this could be done, but not with a
> closed loop SMPS.
> Please correct me if I'm missing something.
> Good day!
> Christopher R. Carlen
Actually it is guile easy to work in critical conduction mode such that you
turn the FET on a short time after sensing zero voltage across the flyback
winding. The control loop leaves the FET on until current builds up in the
power winding depending on output voltage. The loop controls the switching
frequency not PWM. Lower frequency = higher output power. This will result
in ZVS and close to ZCS. This is done quite often for low EMI and high
efficiency. This requires no snubbers.
The control chip need only be a PFC controller, or the UC434N series. Go
to ON Semi and look at their Critical conduction mode PFC IC controllers.
See also http://www.onsemi.com/pub/Collateral/MC33364-D.PDF
In figure 1, if you remove the RCD snubber and add a resonating cap across
across the FET (D to S) and add a delay cap at ZCD you get ZVS operation and
The loop is easy to stabilize with no RHPZ.
piece of cake
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