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From: "Bevan Weiss"
Subject: Re: Bypass capacitor position
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X-Original-Trace: 26 Oct 2002 11:42:06 +1300, news.orcon.net.nz
Date: Sat, 26 Oct 2002 11:42:09 +1300
NNTP-Posting-Date: Sat, 26 Oct 2002 11:42:07 NZDT
"Richard Haendel" wrote in message
> Everyone knows that bypass capacitors should be as close as possible to an
> ic's power and ground leads. That's easy, of course, in the case of some
> PICS (for example) when power and ground are directly opposite to each
> and your using an ic socket that has room for a small capacitor.
> But my question is: can the capacitor be as far away as, say, .2" or .4"
> still be effective (at about 8Mhz)? If the cap can't be equi-distance from
> both leads, should it be closer to positive or ground? Or does it really
> Note that I'm talking about pc boards with through hole devices, not
> breadboads and not smts.
> Richard Haendel
If you think of the IC itself as being a simple MOSFET, which is directly
tied between power and gnd. It will open and close at some digital
frequency, which will of course consist of analog frequencies (please excuse
my differentiation of analog and digital frequencies), these analog
frequencies will depend on the rise time, fall time, period and duty cycle
of the digital signal. Thus you will have a current draw that consists of
many analog frequencies.
If you have long traces connecting that theoretical MOSFET to the supply
(either power or gnd) then you will have a large distance for those many
frequencies to travel, the trace's can be thought of as aerials, they will
radiate the frequencies presented to them at some associated power level
depending on the current draw, hence a low current device will be less
electrically noisy than a similar device of higher current consumption.
That's the EMI issue...
Those same traces are also used to determine what the input signal actually
looks like to the chip. If using standard TTL logic, then you should have
an input '1' as being >2.0V at the receiver, and an input '0' as being
Remembering that this is with relation to the chips own power supply, thus
gnd+2.0V is a '1'.
When you get those large currents being drawn through the power supply
traces you will get some voltage being developed across the impedance (note:
not resistance) of each trace. The voltage dropped will depend on how large
the current through the trace is, and what the impedance of the trace is to
that particular frequency current. If the trace is long, then it will be
primarily inductive, and hence its impedance will increase with an increase
in frequency. This means that the faster your digital signal switches (in
terms of period AND rise time) the more voltage will be lost in just the
traces of the supply. This voltage shows itself as a reduction in the upper
supply voltage and an increase in the gnd voltage.
This is the voltage issue...
If you place a capacitor in parallel with the power supply then you are
allowing high frequency components a low impedance path between gnd and pow,
whilst the lower frequency components can still source their current through
the primary power supply traces, which exhibit a lower impedance to the low
If you look at the levels for the digital logic family again (TTL) then you
note that the low signal '0' can only be 0.8V above the chips GND, and that
the high signal '1' must be greater than 2.0V which is (assuming 3.3V
supply) 1.3V below the positive supply. This gives you a power supply
margin of 0.8V on the GND and 1.3V on the VCC. From this you can see that
it would probably be better to allow any additional voltage loss to occur on
the positive supply rail, as you have more tolerance there. Hence the
capacitor should be placed slightly (note: slightly) closer to the GND pin
of the IC.
However if you're dealing with a 2.5V VCC then you would want it to be
closer to the VCC pin of the IC. It depends too much on what the logic
families voltage levels are to make a generic comment.
That's almost everything...
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