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From: John Popelish
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Subject: Re: Bypass capacitor position
Date: Sat, 26 Oct 2002 21:43:44 GMT
NNTP-Posting-Date: Sat, 26 Oct 2002 17:43:44 EDT
Leon Heller wrote:
> I thought it might be useful to actually create some PCB layouts for the
> various options people have been discussing in connection with this thread.
> They may be perused here:
> I couldn't make make much sense of the ASCII art that has been used.
> Of course, the capacitor could be placed close to the ground pin, as some
> people prefer. Are there any other topologies that could be included?
> A is in line with the recommendation in AoE.
> The gridded layout can include all the other options, I think.
> Which of these is considered optimum, and why?
Thanks. Now we have something specific to talk about.
I am going to guess that E is the closest thing to what Dave has been
describing and is probably the best of the long distribution bus types
you show on the left. But I am sure he will correct me if I am wrong.
A has the highest loop inductance from ground pin, through the cap to
Vcc pin of A to E, so A is probably the worst of these.
B to C are variations between lowest and highest loop inductance. D
has the same loop inductance as E but the bus is in parallel with the
capacitor impedance, while E has the bus less tightly coupled to the
bus and Dave says this is a big plus. I am skeptical.
The gridded example is horrible. :)
Trace the loop that goes from the chip's Vcc pin, through the cap to
the ground pin, if you can.
Suggestions for more variations (after discarding A through C)
Gridded variations: Hook each chip to its cap like example E and then
run both ground and Vcc in both directions and you have a system that
is a fair approximation of a power plane board, though it does use up
a lot of area that could be used for traces. Run a ground and Vcc
trace in close parallel on one side in one direction, and another
close parallel pair on the in other direction on the other side, and
staple them together with a via everywhere same voltage cross. This
is what I would like Dave to criticize. The traces can also bend with
45 degree kinks to pick up a chip pin as they go past, rather than
stubbing off to the chip. Those 90 degree corners don't etch well and
have higher inductance. And the caps can also be hooked up like
example D instead of example E, (but I think Dave likes E a lot
better), but I think, with double gridded supplies, that just lowers
the ability of nearby caps to help stabilize other nodes.
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