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From: firstname.lastname@example.org (Winfield Hill email@example.com)
Subject: Re: Help - Power mosfets - difficult load
Date: 26 Oct 2002 14:49:49 -0700
References: <firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org> <email@example.com> <3DB81206.E28CA99F@rica.net> <firstname.lastname@example.org> <email@example.com>
NNTP-Posting-Date: 26 Oct 2002 21:49:49 GMT
firstname.lastname@example.org (Bill Allison) wrote ...
> Thanks for that really lucid explanation and for your time and
> trouble. And I got your post by E-mail first - this reply is the later
> and slightly fuller.
> One or three comments…
> 1) Considering fet temperature rise, I have in my favour the fact that
> the motor will be powered up for around 10 seconds at most, every 5
> minutes or so at worst.
10 seconds is in your favor, but thermally 5 minutes is forever. :-)
> 2) Your calculations are based on the motor's winding resistance i.e.
> on the current that would flow into a stalled motor, but the average
> current will surely be less when the motor is rotating? The motor's
> spec says 380A stalled, 70 to 80A with rated load. And stall current
> will only flow for the briefest of moments at start-up (the motor will
> always be started with no load other than brush and bearing friction).
We experienced engineers hate to see one of our design fail and have
to fall back on an excuse (the motor was jammed, cable caught, etc.)
so our habit is to try to make the design invincible. It's true this
often leads so serious overdesign. In your case the high current may
normally only last 0.1 to 0.25 second or so. However if you look at
the FET's Transient Thermal Impedance curves you'll see the short-term
thermal-mass advantage is gone by the time 100ms has passed, and you're
in the long-term thermal resistance.
Perhaps an answer is to employ a say 50 to 75A circuit breaker, which
should not kick out during the short starting transient, nor during a
short time at or just above rated current.
> 3) Your calculations are also based on switching the fet as fast as it
> is capable of. Is there a possibility that I might need to use slower
> rise and fall times to prevent the amplitude of transients (due to
> load and stray inductances) exceeding drain to source limits? That
> would be at the expense of switching losses and might make switching
> frequency a consideration? The idea is from IRF app note AN-936
I did the calculation with a modest 1.5A gate drive for a very slow
75ns switching speed just to allow you relaxed wiring rules. Even at
this low speed and 20kHz switching the switching losses were only 2W
(I wrote 1W, but had forgotten there are two transitions per cycle).
The point I intended was that with a decent level of gate drive, don't
worry about switching losses, unless you're running above say 100kHz.
If you decide to run at 50Hz and to use very low gate drive, such as
50mA out of a 555, shared 25mA each among two FETs, then at turnoff
the FETs will experience a high transient power, but they're rugged
devices and may be able to handle such mistreatment. We can predict
a 5us turnoff time for 25mA drive, and 3.5mJ of heating in the 5us,
which isn't too bad. But I suggest more aggressive gate drive.
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