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From: "Bevan Weiss"
References: <191C91BDFE8ED411B84400805FBE794C2DA011B9@pfs21.ex.nus.edu.sg> <email@example.com> <firstname.lastname@example.org> <email@example.com>
Subject: Re: PCB routing
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X-Original-Trace: 27 Oct 2002 11:48:45 +1300, news.orcon.net.nz
Date: Sun, 27 Oct 2002 11:48:49 +1300
NNTP-Posting-Date: Sun, 27 Oct 2002 11:48:46 NZDT
"Nico Coesel" wrote in message
> "Bevan Weiss" wrote:
> >"chris" wrote in message
> >> "Alex C" wrote in message
> >> > Hi,
> >> > How do we determine thickness of line width to route when dealing
> >> > or signal traces on a PCB? Does the location ( either surface layer
> >> > sandwitch in between dielectric) changes the properties of the
> >> > the trace?
> >> >
> >> > normally what is the size of a min via drill to use for power or
> >> > also what is the clearance to use for these via if it's surrounded by
> >> > plane?
> >> >
> >> > thanks for your expertise.
> >> Hi, it all depends on your pcb manafacturer, they will normaly specify
> >> the limits.Generaly , the min space should equal the min trace width,
> >> the wider the better.Power traces should be laid out carefully, don't
> >> let the autorouter do it,They don't have to be very wide unless you
> >> have heavy current devices, 0.6mm is usually sufficient.
> >0.6mm isn't very wide at all, that's less than 25mil. I would say that's
> >only good for a couple of hundred milliamps max...
> >I'd just go with a flood fill of ground on one side of the board and
> >on the other side. If you're designing a multilayer board this changes
> Copper poors only work a bit for shielding, not for distributing
> power. On a double sided board you'll still need good power routing (I
> always route power as a maze). There are to many intersections in a
> copper poor on a double sided board to have adequate power
> distribution (unless you're lucky...).
A copper pour has the same characteristic as a copper plane, it will have a
lower resistance than a plain trace as it has a larger current distribution
area, it will also suffer less from skin effect as it has a larger surface
area, it will have less inductive reactance as the current density is lower.
If you have very thin areas of pour (ie a thin trace poured between two
other conductors) then this will increase the total impedance of the GND
connection to any devices on the non supply side of that thin trace of pour,
however this would be the case if you were routing a trace maze style to
those IC (or other device) pins. You still have to ensure that the traces
(where the pour doesn't get to flow much) are adequatly sized to prevent
overheating etc, however the problem becomes much less and much more obvious
to see. Just look for all the areas where two copper fills are joined with
a thin trace and see whether you could move other traces to ensure that
trace can be made larger (ie into a better fill).
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