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From: "Bevan Weiss"
Subject: Re: Bypass capacitor position
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X-Original-Trace: 27 Oct 2002 15:19:07 +1300, news.orcon.net.nz
Date: Sun, 27 Oct 2002 15:19:12 +1300
NNTP-Posting-Date: Sun, 27 Oct 2002 15:19:08 NZDT
"John Popelish" wrote in message
> Leon Heller wrote:
> > I thought it might be useful to actually create some PCB layouts for the
> > various options people have been discussing in connection with this
> > They may be perused here:
> > http://www.geocities.com/leon_heller/bypass.html
> > I couldn't make make much sense of the ASCII art that has been used.
> > Of course, the capacitor could be placed close to the ground pin, as
> > people prefer. Are there any other topologies that could be included?
> > A is in line with the recommendation in AoE.
> > The gridded layout can include all the other options, I think.
> > Which of these is considered optimum, and why?
> Thanks. Now we have something specific to talk about.
> I am going to guess that E is the closest thing to what Dave has been
> describing and is probably the best of the long distribution bus types
> you show on the left. But I am sure he will correct me if I am wrong.
> A has the highest loop inductance from ground pin, through the cap to
> Vcc pin of A to E, so A is probably the worst of these.
> B to C are variations between lowest and highest loop inductance. D
> has the same loop inductance as E but the bus is in parallel with the
> capacitor impedance, while E has the bus less tightly coupled to the
> bus and Dave says this is a big plus. I am skeptical.
> The gridded example is horrible. :)
> Trace the loop that goes from the chip's Vcc pin, through the cap to
> the ground pin, if you can.
> Suggestions for more variations (after discarding A through C)
> Gridded variations: Hook each chip to its cap like example E and then
> run both ground and Vcc in both directions and you have a system that
> is a fair approximation of a power plane board, though it does use up
> a lot of area that could be used for traces. Run a ground and Vcc
> trace in close parallel on one side in one direction, and another
> close parallel pair on the in other direction on the other side, and
> staple them together with a via everywhere same voltage cross. This
> is what I would like Dave to criticize. The traces can also bend with
> 45 degree kinks to pick up a chip pin as they go past, rather than
> stubbing off to the chip. Those 90 degree corners don't etch well and
> have higher inductance. And the caps can also be hooked up like
> example D instead of example E, (but I think Dave likes E a lot
> better), but I think, with double gridded supplies, that just lowers
> the ability of nearby caps to help stabilize other nodes.
I believe that my opinion of the optimum placement is missing from that
It involves a SMT cap (which have superior, low, inductance values compared
to throughholes) on the reverse side of the board, the traces are
multilayer hence there should be a top and bottom side of the board. Have
the TH (through hole) DIP with it's power connections (ie VCC and GND)
connected to the main suply rails. Then on the reverse side of the board
place a SMT cap such that it lies as close as possible between the power and
gnd connections, ie in the middle of the reverse image of the DIP. If
you're dealing with entirely SMT components, then placing a via in the
actual GND/VCC pad of the chip and then having the via passing the
connections to the cap on the reverse side of the board.
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