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From: email@example.com (CB)
Subject: Re: Help with 1394a design with TI TSB43AA82A
Date: Mon, 28 Oct 2002 03:06:58 GMT
Organization: CompuServe Interactive Services
NNTP-Posting-Date: Mon, 28 Oct 2002 03:03:38 +0000 (UTC)
X-Newsreader: Forte Free Agent 1.21/32.243
Best of Luck, as a small consulting firm we just turned down a job
which required a firewire device interface , initial order of 400
systems with many more possible. I tried "working" with both TI and
Philips since both companies have possible silicon solutions, in both
cases I was told I would not receive any assistance from the company,
no design kits, boards, or even questions answered unless I could
place an order for something like 100,000 chips ... mmmmmm .... CB
On Wed, 23 Oct 2002 18:11:18 GMT, "gurtler" wrote:
>I am designing a PCB that will use 1394a (Firewire) communication for high
>speed data transfer to a host (PC) port. The TI device (TSB43AA82A)
>(hereafter "Device") is an integrated Link/PHY device and can be interfaced
>to a MCU. My PCB will be a peripheral device. The datasheet is located at
>I am having trouble understanding the handshaking between the MCU and the
>Device. The handshaking timing diagram for the parallel mode of operation
>is given in Figure 10-1 and the timing data for the figure is Table 10-1.
>There is essentially no narrative describing the figure and the table and
>frankly I am having trouble making sense of it. If anyone is familiar with
>this device or thinks they know how to interpret it, I would appreciate
>hearing from them. I have attempted to get technical help from TI but since
>I am not Sony, or Cannon, or some giant firm, they won't give me the time of
>day. TI even hinted that they don't give out complete data because they
>want to support (i.e. get money from ) customers!
>My problem is clearly understanding exactly when address and data are
>acquired in Figure 10-1 with respect to XWR/XRD. Does a READ occur on the
>falling edge of XRD/XWR? At least then the address is valid, but the read
>data might not be available for 160ns (see table trd_da) - does that make
>sense? Or does it take place on the rising edge of XRD/XWR? At least then
>the read data is present, but there is no daddress data at that time!
>Likewise - when does a write occur?
>Maybe the addressing and read/write protocol is common and assumes knowledge
>of which I am unaware, but I don't get it.
>If someone has experience/knowledge of this device - I would appreciate a
>narrative explaining how to interpret this diagram.
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