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From: Fred Bloggs
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Subject: Re: Help with 1394a design with TI TSB43AA82A
Date: Tue, 29 Oct 2002 13:18:55 GMT
NNTP-Posting-Date: Tue, 29 Oct 2002 05:18:55 PST
Organization: EarthLink Inc. -- http://www.EarthLink.net
> I am designing a PCB that will use 1394a (Firewire) communication for high
> speed data transfer to a host (PC) port. The TI device (TSB43AA82A)
> (hereafter "Device") is an integrated Link/PHY device and can be interfaced
> to a MCU. My PCB will be a peripheral device. The datasheet is located at
> I am having trouble understanding the handshaking between the MCU and the
> Device. The handshaking timing diagram for the parallel mode of operation
> is given in Figure 10-1 and the timing data for the figure is Table 10-1.
> There is essentially no narrative describing the figure and the table and
> frankly I am having trouble making sense of it. If anyone is familiar with
> this device or thinks they know how to interpret it, I would appreciate
> hearing from them. I have attempted to get technical help from TI but since
> I am not Sony, or Cannon, or some giant firm, they won't give me the time of
> day. TI even hinted that they don't give out complete data because they
> want to support (i.e. get money from ) customers!
Stop your whining and figure the damned thing out for yourself.
> My problem is clearly understanding exactly when address and data are
> acquired in Figure 10-1 with respect to XWR/XRD. Does a READ occur on the
> falling edge of XRD/XWR?
NO! It is clear from the diagram that RD is performed on the low-to-high
transition of WRD.
> At least then the address is valid, but the read
> data might not be available for 160ns (see table trd_da) - does that make
That 160ns refers to the delay of valid data from the high-to-low edge
of XRD. The address is latched into the USB controller on that edge also
and can be lifted 0ns after that.
> Or does it take place on the rising edge of XRD/XWR? At least then
> the read data is present, but there is no daddress data at that time!
Yeah- right! That's what it shows. The address is latched by the USB and
is no longer required for RD data.
> Likewise - when does a write occur?
The WR occurs on the low-to-high transition of XWR. Fig 10-1 is screwed
up. See the MUX Mode figure for the set-up and hold times.
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