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Subject: Re: Ground Bounce (SSN)
Date: Thu, 31 Oct 2002 10:54:48 -0800
Organization: MindSpring Enterprises
X-Server-Date: 31 Oct 2002 19:04:53 GMT
X-Newsreader: Forte Free Agent 1.92/32.572
On Wed, 30 Oct 2002 13:08:23 -0500, "Douglas J Petican"
>I'm using a 74ALS541 and 74ALS573A together to implement a bidirectional
>databus. The 573 latches the output data (LE=0) when the 541 is used to
>read input. The 541 is tristated (CS=1) when data is being written to the
>573. To read data I set LE=0 and CS=0. To write data I set CS=1 and LE=1.
>The circuit works great except that on the ZH transition of the 541 with
>greater than 3 high outputs creates ground bounce which causes the LE on
>the 573 to temporarily go from low to high.
00001111 This would be an problem data pattern.
11110000 This wouldn't be a problem data pattern.
If this is the case, more than likely this isn't ground bounce.
You have the same currents involved in both cases.
This lead me to believe it to be more of a:
1) Localized I * R problem (or poorly constructed board.)
2) Miss wired
3) Bad IC
4) You have a problem with timming, so you have two outputs on at the
same time. (One high when the other is low.)
>My power supply voltage is 5V and I'm using a 3M style prototyping board.
>I have power and ground running along both top and bottom. I already have a
>10uF tantalum cap in paralell with a 1uF cap from Vcc to Vss. Are these good
>values? What about a 2-3pF between Vss pins and the ground rail?
You might want to consider rebuilding the project. (I don't use plug
boards anymore for my prototype.) I would place the IC upside down on
top of a sheet of solid copper clad board (I have heard this called:
"Dead Bugging") using 3M double back tape to hold the parts to the
board. Make the solid sheet of copper the ground and cut strips from
this board to make up your power rails. Use the double back tape to
hold the power rails to the board. Allow enough room from your power
rails to the parts, so you can easily get bypass caps between them.
The bypass caps should be solder in as close as you can get them to
the power pins, thus keeping the leads as short as you can get them.
(I will sometimes use chip caps and lean them up against the VCC pin
and ground plane.) The two values you have chosen are pretty good
ones. But, I would place a pair of both, on the two parts. (For a PCB,
I would consider 2.2 ufd instead of the 10 ufd, in a lead less frame.)
>The caps on the Vcc pins run from the pin to ground on the top rail while the
>Vss pins connect to ground on the bottom rail. Is this correct or should I
>connect the 10uF/1uF filter caps across the chip from Vcc pins to Vss pins?
>I'm also considering switching to CMOS and using a 12V power supply to
>increase the noise margin.
>Any other comments or suggestions would be greatly appreciated.
>Thanks, Doug Petican
I have seen a few good designs go into the trash can, because the were
not constructed the right way in the test lab.
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