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From: email@example.com (Richard_Gurtler)
Subject: Re: Help with 1394a design with TI TSB43AA82A
Date: 6 Nov 2002 09:10:45 -0800
NNTP-Posting-Date: 6 Nov 2002 17:10:45 GMT
Fred Bloggs wrote in message news:<3DBE8AE4.firstname.lastname@example.org>...
> gurtler wrote:
> > I am designing a PCB that will use 1394a (Firewire) communication for high
> > speed data transfer to a host (PC) port. The TI device (TSB43AA82A)
> > (hereafter "Device") is an integrated Link/PHY device and can be interfaced
> > to a MCU. My PCB will be a peripheral device. The datasheet is located at
> > http://www-s.ti.com/sc/psheets/slls512a/slls512a.pdf
> > I am having trouble understanding the handshaking between the MCU and the
> > Device. The handshaking timing diagram for the parallel mode of operation
> > is given in Figure 10-1 and the timing data for the figure is Table 10-1.
> > There is essentially no narrative describing the figure and the table and
> > frankly I am having trouble making sense of it. If anyone is familiar with
> > this device or thinks they know how to interpret it, I would appreciate
> > hearing from them. I have attempted to get technical help from TI but since
> > I am not Sony, or Cannon, or some giant firm, they won't give me the time of
> > day. TI even hinted that they don't give out complete data because they
> > want to support (i.e. get money from ) customers!
> Stop your whining and figure the damned thing out for yourself.
> > My problem is clearly understanding exactly when address and data are
> > acquired in Figure 10-1 with respect to XWR/XRD. Does a READ occur on the
> > falling edge of XRD/XWR?
> NO! It is clear from the diagram that RD is performed on the low-to-high
> transition of WRD.
> > At least then the address is valid, but the read
> > data might not be available for 160ns (see table trd_da) - does that make
> > sense?
> That 160ns refers to the delay of valid data from the high-to-low edge
> of XRD. The address is latched into the USB controller on that edge also
> and can be lifted 0ns after that.
> > Or does it take place on the rising edge of XRD/XWR? At least then
> > the read data is present, but there is no daddress data at that time!
> Yeah- right! That's what it shows. The address is latched by the USB and
> is no longer required for RD data.
> > Likewise - when does a write occur?
> The WR occurs on the low-to-high transition of XWR. Fig 10-1 is screwed
> up. See the MUX Mode figure for the set-up and hold times.
Thanks for the response (I had given up on a response - sorry for the
delay in checking again).
As for whining - I did try to figure it out, but before commiting time
and money to a board I wanted to be sure I understood the timing.
Your last comment - "Fig 10-1 is screwed up" - is my feeling too.
How are you so sure of your opinions? You refer to the device as a
"USB controller" but this is Firewire. Protocols may be different.
Have you worked with this device? Or are your opinions educated
guesses? The TI documentation is really skimpy.
One thing I was confused on is the use of XRD/XWR in Figure 10-1. I
had been thinking this meant a single pin that functioned as a read
state when XRD/XWR was high, and a write state when XRD/XWR was low -
a convention that is used often on devices but not necessarily for
memory access situations. My mistake - because of unfamiliarity with
the device. I later realized there is an XRD pin and an XWR pin. So I
guess Figure 10-1 refers to timing for either XRD or XWR and the
difference in behavior is indicated by the read or write data.
But I would have thought that when the device is active, but not in a
read or write mode, that XRD and XWR would be held low. Nothing
indicates that XRD or XWR are active low. Then I would guess that the
address would be latched on the leading edge (low to high) and the
data valid on the trailing edge (high to low. Figure 10-1 indicates
the opposite (if I assume the write data actually is valid at the
low-high transition, contrary to the figure and table data).
I have a hard time using data from the multiplex mode because of the
difference in use.
You say Figure 10-1 is "screwed up." Since I wish to use parallel
mode, how would you correct the figure and table? When a read is
desired, is XWR held low or high? Are XRD and XWR active low like the
figure might imply?
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