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From: "Bill Sloman"
Subject: Re: Maximum load capacitance that 4000 family cmos devices can handle.
Date: Wed, 6 Nov 2002 23:20:26 +0100
Organization: Planet Internet
NNTP-Posting-Date: 6 Nov 2002 23:20:11 GMT
X-Newsreader: Microsoft Outlook Express 6.00.2800.1106
"John Larkin" wrote in
> On Wed, 6 Nov 2002 13:12:44 -0500, "KILOWATT" spam"@SOFTHOME.NET> wrote:
> >Hi everyones. Thanks to read
> >On the net in many .PDF files, and also in
> >mr. Lancaster's CMOS Cookbook...it is said
> >that a fanout of 50 gates max is recommended
> >to prevent slow transitions. Since each inputs of
> >the 4000 family is typically 5 nanofarad and a
> >maximum of 50 gates is recommended,i assume then
> >that 250pF is the maximum allowable capacitance
> >an output can drive. I want to drive a 1500pF
> >load (the gate of an n-channel power mosfet). The
> >circuit would be rather ON or OFF for long periods
> >of times(minutes!) so transition time seems
> >irrevelant here.
> >What i'm worrying about is the 10mA limit for such
> >devices,and i don't want to latch up the IC and then
> >destroy it because of too much load capacitance.
> >Anyone can tell me if a 1500pF gate-source capacitance
> >from a power mosfet transistor is too much for a 4000
> >family device...what are the limits? TIA
> No problem, no limits. The edges just get slower as the cap load
There is one extra potential problem area if you are running 4000 series
logic at close to its maximum allowable supply voltage - if the edge
transitions are very slow, the inputs being driven by the slow edge can
spend quite a long time in a state where both the n-channel the p-channel
transistors are turned on. This doesn't amount to a short circuit, but you
could get the gates hot enough to fry the circuit if you were dead unlucky.
The current spikes on the supply rail get pretty big too, and the gates are
spending a long time in the condition where they will amplify any noise on
the drive waveform by a factor of ten or so.
It is a situation you want to avoid.
Bill Sloman, Nijmegen
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