The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
From: John Popelish
Organization: This space not available for advertising.
X-Mailer: Mozilla 4.7 [en] (Win98; U)
Subject: Re: Maximum load capacitance that 4000 family cmos devices can handle.
Date: Thu, 07 Nov 2002 00:19:16 GMT
NNTP-Posting-Date: Wed, 06 Nov 2002 19:19:16 EST
Bill Sloman wrote:
> There is one extra potential problem area if you are running 4000 series
> logic at close to its maximum allowable supply voltage - if the edge
> transitions are very slow, the inputs being driven by the slow edge can
> spend quite a long time in a state where both the n-channel the p-channel
> transistors are turned on. This doesn't amount to a short circuit, but you
> could get the gates hot enough to fry the circuit if you were dead unlucky.
> The current spikes on the supply rail get pretty big too, and the gates are
> spending a long time in the condition where they will amplify any noise on
> the drive waveform by a factor of ten or so.
> It is a situation you want to avoid.
But this is only a problem if you use the slowed output to also drive
a CMOS input. As long as it drives only an external device, this
problem does not arise. Or am I missing something?
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup