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From: firstname.lastname@example.org (Bill Sloman)
Subject: Re: Maximum load capacitance that 4000 family cmos devices can handle.
Date: 7 Nov 2002 15:07:02 -0800
References: <6Xcy9.email@example.com> <3DC9B188.942E53DE@rica.net>
NNTP-Posting-Date: 7 Nov 2002 23:07:02 GMT
John Popelish wrote in message news:<3DC9B188.942E53DE@rica.net>...
> Bill Sloman wrote:
> > There is one extra potential problem area if you are running 4000 series
> > logic at close to its maximum allowable supply voltage - if the edge
> > transitions are very slow, the inputs being driven by the slow edge can
> > spend quite a long time in a state where both the n-channel the p-channel
> > transistors are turned on. This doesn't amount to a short circuit, but you
> > could get the gates hot enough to fry the circuit if you were dead unlucky.
> > The current spikes on the supply rail get pretty big too, and the gates are
> > spending a long time in the condition where they will amplify any noise on
> > the drive waveform by a factor of ten or so.
> > It is a situation you want to avoid.
> But this is only a problem if you use the slowed output to also drive
> a CMOS input. As long as it drives only an external device, this
> problem does not arise. Or am I missing something?
Not at all. The OP only talks about drivng an external device, but
cheapskates the world around have this tendency to see a logical level
waveform and use it to drive logic as well, no matter how horrible the
edges look. I was just getting in a pre-emptive strike.
Bill Sloman, Nijmegen
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