From: Winfield Hill
Subject: Re: Amplifying small DC signal with large DC bias...
Date: 11 Nov 2002 07:40:09 -0800
Organization: Rowland Institute
X-Newsreader: Direct Read News 4.10
Mike Deblis, email@example.com wrote...
> I'm after a few ideas - I have a DC signal - about 4 volts, on
> which is superimposed a small (few uV) DC/VLF signal. I need
> about 40dB amplification to reliable use the wanted signal, but
> how to I remove the 4V DC bias to prevent the opamp clipping?
Hi Mike. One technique would be to create a precise adjustable
reference voltage, with a fine-adjust capability and then amplify
the difference with a high-gain differencing or instrumentation
amplifier. But since the dc level you describe is approximate but
stable, a second technique may prove more useful. Our book, "The
Art of Electronics," has exactly the circuit you need on page 393,
called an "Autonulling dc laboratory amplifier."
"This gadget lets you 'freeze' the value of the input signal,
amplifying any subsequent changes from that level by gains of
exactly 10, 100, or 1000."
This circuit serves as a testbed for the introducing important
materials in our Precision Circuits chapter. There are 12 pages
of detailed discussion showing the design calculations behind the
autonulling amplifier circuit. I suggest that you borrow a copy
and study these pages. Here's an abbreviated form of the circuit.
. buffer ___||___
. INPUT \___ | _ |
. protection --|___|--/\/\--+--| \ | OUTPUT
. | >--+----------+----
. ,----------------|_/ |
. | 10uF 1.0k
. offset ,--||---, ,-\/\/--, |
. range | _ | | gnd |
. | | / |__|____ __|__ _____|
. ,-------+----+-< |__ | |_| |_|
. | \_| | | |_______|______ logic
. | ,--/\/--, gnd | control
. | | _ | | low-leakage
. '-/\/-+--| \ | | FET switches
. | >-+-/\/-, |
. gnd --|_/ | |
. | | |
. | |<-' drift-nulling pot
. |_| leakage-compensation
Whenever you activate the FET switches an integrator rapidly
zeros the output by taking on the input's value at that instant.
Thereafter a high-gain output stage amplifies any changes in the
input. Several tricks are employed to eliminate leakage currents
in the cancel/hold FET switch and the integrator's 10uF capacitor.
Looking at the design, I'd make some changes in the circuit these
days; if you're interested we could review them in this thread.