The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
From: "Dave Fenner"
Subject: Re: CMOS Design Problem
Date: Wed, 13 Nov 2002 02:47:18 -0000
NNTP-Posting-Date: 13 Nov 2002 02:49:13 GMT
X-Newsreader: Microsoft Outlook Express 6.00.2600.0000
"Justin Time" wrote in message
| I have cascaded a series of D-type flip-flops so the Q output of
| feeds the Data input of the next. Under carefully controlled
| conditions it works but has a problem. Waving my hand within 6
| of the circuit board triggers the flip-flops to a high state.
| Sometimes one or two... sometimes ten at once. I suspected an
| inadequately filtered 5 vdc source, but after changing to a 12
| gel cell battery with a 5 volt voltage regulator, the problem
| persisted. I experimented with voltages ranging from 2.6 volts to
| volts without success.
| I now suspect "noise" from overhead lights or perhaps capacitance
| straying into the circuit from the wires that connect the circuit
| Vcc, GND, Clear and Clock.
| Is there a way to isolate my circuit design from ambient stray
| capacitance / noise? At this time I have not inserted a clock
| but have pulsed the input manually in an attempt to pursuede the
| registers to store the 1 s I have generated into memory.
| The design works well on paper, but on the bench it is driving me
| nuts. Any suggestions would be helpful from anyone with CMOS
| experience. Respectfully, Justin
Is your entire circuit floating? Tie 0V to earth.
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup