The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
X-Mailer: Mozilla 4.79 [en] (Win98; U)
Subject: Re: Querry, Kick Starting Crystal Oscilator.
References: <3DCA905A.59FD928B@mmm.com.DELETETHIS> <3DCC9A71.7DF3C3A9@mfi.net>
NNTP-Posting-Date: Wed, 13 Nov 2002 14:27:27 GMT
Organization: AT&T Broadband
Date: Wed, 13 Nov 2002 14:27:27 GMT
Tim Shoppa, Winfield Hill wrote:
>> As the crystal voltage increases the logic-level rise and fall
>> times will decrease. Tim, I wonder what you would see for the
>> risetime on pin 10 over time at startup. The counter has more
>> inverter stages to help, you can inspect the next one at pin 9.
> Measured on pin 10:
> 50 ms after startup: 5.2 us risetime
> 100 ms after startup: 2.8 us risetime
> 200 ms after startup: 1.8 us risetime
> 300 ms after startup: 1.5 us risetime
> 10 sec after startup: 1.2 us risetime
> Looking at the amplitude at pin 11, that does take a full second to
> reach max amplitude (about 2V Pk-Pk).
> The pin 9 output seems to have a pretty good square wave on it within
> 20 ms after startup.
Perhaps you read my response to Roy McCammon elsewhere in this thread.
Would it be possible to run the same experiment with the circuit values
suggested in that post and see if start up response is improved (10M,
33k, 220p and 22p)?
Here is the meat of that post for reference. -- analog
During the start up of a well designed crystal oscillator circuit, loop
gain at the point of 360 degrees phase shift should greatly exceed
unity. The high gain forces system poles well into the right half plane
for the low circuit Q necessary to allow the quick imposition of near
steady state operating conditions onto the crystal. With low starting Q,
oscillations build up rapidly until amplifier output saturation is just
deep enough to pulse width modulate average loop gain down to precisely
one. (With care you should be able to observe the output waveform start
as a growing sine wave that clips ever more heavily until it becomes
virtually a square wave.)
I would suggest the following circuit for your application.
| 10M | unbuffered
| | ~ | Ro gate gain
+---| >o---+----\/\/\/---+ 10 min
| | + 33k | 20 max
| C0 |
| 1.7pF | / typical params
| | > for 32kHz xtal
| L1 C1 R1 | \ (Q=12k)
| 6kH 4fF 100k |
Ci === 22p Co === 220p
The bias resistor forces the gate into the linear mode, but must not be
too small or it will kill circuit Q because of the very high impedance a
32kHz crystal presents to the input node of the gain stage. Trace runs
on this node should be very short and free of any conductive contamina-
tion. To give you an idea how sensitive to loading this node is, the
circuit will probably not operate at all with a bias resistor below 3.3M
ohms, yet a 10 M ohm resistor may be too big to overcome stray leakages
and properly bias the gate into its linear mode.
Since phase shift through the crystal can at best only approach 180
degrees and is only 90 degrees at the point of maximum voltage gain, the
33k resistor together with the 220pF capacitor serves to provide enough
extra phase shift around the loop to allow the crystal to operate near
this point of maximum voltage gain (at which its phase shift will be
about 120-130 degrees). This network has the added advantages of
limiting the power dissipated in the (typically) delicate 32kHz crystal
to under 10uW (for a 5 volt system) as well as decoupling the gate's
output from having to directly drive the 220pF of capacitance.
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup