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Subject: Re: Historical question: negative feedback and the op amp
X-Newsreader: Microsoft Outlook Express 5.50.4920.2300
Date: Thu, 14 Nov 2002 07:19:08 GMT
NNTP-Posting-Date: Thu, 14 Nov 2002 02:19:08 EST
Organization: Cox Communications
"Chuck Simmons" wrote in message
> Mike wrote:
> > "Chuck Simmons" wrote in message
> > news:3DD27F3D.667A4D75@webaccess.net...
> > > Mike wrote:
> > > >
> > > > "Jeroen" wrote in message
> > > > news:GyuA9.80964$I6.email@example.com...
> > > > >
> > > > >
> > > > > In case of IIR filters, feedback reduces the number of
> > > > needed.
> > > > > In this case feedback isn't a thing that slows things down.
> > > >
> > > > Actually, it does slow down the maximum operating frequency. I can
> > pipeline
> > > > an FIR filter almost without limit, and obtain very high clock
> > frequencies.
> > > > In an IIR filter, the maximum operating frequency is often
> > the
> > > > feedback loop. In the general case, the feedback term has to be
> > > > calculated in one clock cycle.
> > >
> > > An IIR can produce output with one multiply and one add at the arrival
> > > of the sample for that iteration. Does anyone not do this? It is
> > > This means that there is no difference in output speed of an FIR
> > > an IIR with fixed sampling and infinite speed arithmetic.
> > Yes, but if your arithmetic isn't infinite speed, then there's a
> > limitation due to the feedback loop in the IIR filter. As a result, the
> > clock rate can be significantly faster than for an IIR filter with
> > equivalent word widths.
> I don't see this at all. Forgetting that an FIR filter cannot be used as
> a compensator for controlling a dynamical system of order two or
> greater, exactly the same amount of time is available for computation at
> fixed sample rate for both. For both the IIR and the FIR, the
> computation is a difference equation but the FIR has no output terms in
> it. In the control situation, the pipeline used for the FIR must be
> short because, in most cases, the nth output from the controller depends
> on the nth input. If not, the controller will fail anyway unless made
> even more complex than the high order already required to control a
> dynamical system because of delay. Delay requires estimation which
> simply means the order goes up. Estimators are of limited use because of
> errors introduced from the outside that are unknown to the estimator
> which is designed for perfect dynamics (what else?).
Okay, here's what I'm thinking: the FIR output is given by
y(k) = a0*x(k-1) + a1*x(k-2) + .... + aN-1*x(k-N)
For the sake of simplicity, let's ignore the multiplications for this
example. Once the multiplications are completed, I still have to find the
sum of the products. If I'm running at a fast clock rate, there's not time
to do all these additions, but I can start pipelining. On the first clock
cycle, I'll add adjacent terms in pairs:
b01(k) = a0*x(k-1) + a1*x(k-2)
b23(k) = a2*x(k-3) + a3*x(k-4)
On the next clock cycle, add the b terms in pairs:
c02(k) = b01(k) + b23(k)
c46(k) = b45(k) + b67(k)
Keep going until the process is complete. Each level is registered; the c(k)
computation takes place at the same time that the b(k+1) terms are being
We can go further: if there's inadequate time to complete the additions in
one clock cycle, they can be pipelined as well. I built an FIR a few years
ago that used a Booth multiplier with a latency of three clock cycles, and a
tree of adders with latency of two clocks at the top of the tree, and three
clocks at the bottom (as the word widths increased). The overall latency was
something like 12 clock cycles from the time that the last data word entered
In the IIR filter, the y(k) result is needed during the next clock cycle,
and there's no practical way to delay it in the general case.
-- Mike --
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