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Subject: Re: PLD 5V tolerant I/O
Date: Fri, 15 Nov 2002 11:59:50 -0000
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"Tim Hubberstey" wrote in message
> markp wrote:
> > Hi All,
> > I have a question regarding 5V tolerant I/O on PLDs. The spec I have for
> > this 4000 series Lattice part says that the inputs can tolerate 5V, and
> > leakage current is specified for this but only with the output section
> > turned off. Is it possible to use a pull-up on the pin to 5V? What
> > to the output voltage when driving a signal pulled up to 5V (i.e. does
> > high drive FET clamp to 3.3V, or does the diode start conducting, or
> > the FET turn off and allow the voltage to climb to 5V?).
> I would expect that the top (P-channel) FET will clamp the output to the
> Vccio rail when driving a '1', regardless of your pull-up. If you want
> the output to swing to 5 V, you need to create an open-drain output. You
> can do this by driving a constant '0' to an output and driving the
> output's tristate control with the inverted output signal (assuming
> active-high tristate controls). This will have a slower rise time than
> an actively driven output.
There's a problem with the classic complementary output stage in the
parasitic diode of the top FET. The signal is bi-directional, which means
this diode must somehow be isolated when the driver is off in order for the
input to be 5V tolerant. There could well be a FET in line with the signal
that behaves like a switch in that it is usually on all the time unless the
pin voltage goes above 3.3V, in which case it turns off (similar to
QuickSwitches, see app note below). This would provide 5V tolerance on both
input and output while allowing a fast drive up past the TTL Voh.
> However, the output meets TTL specifications without pull-ups so unless
> you need to drive to 5 V for some other reason (like input power
> consumption), I'd forget the pull-up.
In this particular application I am interfacing to a 5V bus that may have
pull-ups to 5V already on it. I need to be sure I can drive this bus to TTL
levels from the PLD without excessive current. I'm just trying really to
understand the output structure of the PLD!
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