The Cyber-Spy.Com Usenet Archive Feeds Directly
From The Open And Publicly Available Newsgroup
This Group And Thousands Of Others Are Available
On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic,
Opinions Or Content Posted To This Or Any Other
Newsgroup. This Web Archive Of The Newsgroup And
Posts Are For Informational Purposes Only.
From: email@example.com (Adam Seychell)
Subject: Re: Problems with MOSFET drivers
Date: 17 Nov 2002 17:52:18 -0800
References: <firstname.lastname@example.org> <email@example.com>
NNTP-Posting-Date: 18 Nov 2002 01:52:18 GMT
Mike Poulton wrote:
> On 16 Nov 2002, firstname.lastname@example.org (Adam Seychell) said:
> The core is CWS Bytemark material 77 (u=2000). The windings are 28awg
> kynar insulated wire-wrap wire. Four wires were twisted together and
> wound as the seondaries. Four more wires were similarly twisted and
> wound interleaving with the first to form the primary, skipping across a
> few turns occasionally so that both windings cover the whole toroid.
> All four primary wires are in parallel. Your idea is better.
The transformer is criticle in this aplication as you noticed the
horrible mess on the output. Some of the other replies you got gave
possibilities of whats happening.
>>You probably need something more clever like a phase locked VCO to
>>control the bridge. That way you can guarantee 50% duty cycle and
>>frequency can never accidentally get out of range to cause
>>going up in smoke but rather just quietly oscillates out of tune.
> Yes. I had an idea last night. I think the way to do this will be to
> use a VCO to control the primary switching. The VCO will be controlled
> by a circuit that senses primary current (averaged over 0.1 seconds or
> so). It will vary the drive frequency over a range of about 10% to
> maximize current. This will correspond to the resonant frequency, where
> input impedance is minimized.
That method of control cannot stabilize to the resonant frequency
since the magnitude of the current falls off either side of Fo. You
must have phase information.
I'd look at getting a CMOS 4046 PLL to lock in on the primary current
using a current transformer. And limit the VCO to narrow frequency
range say 500kHz ~ 700kHz.
But first get the gate driving problem fixed and don't even start to
worry about feed back or loop control. You may need to totally re-plan
your entire driver/transformer/bridge setup. If you want the ultimate
gate drive transformer then use 4 windings of RG178 coax over a say
30mm E core. Connect all shields together for primary and each inner
conductor go to a FET. I think the only leakage inductance here will
be outside connections to the FETs and driver. Put gate resistors
also, at least while developing. The only disadvantage is reduction in
efficiency of the bridge but that's not your priority at the moment
and can be optimised at a latter time. Use 3A SMD schottky diodes
across the output of driver to supplies in order to stop reverse
currents (they must be close to the drivers or they have little
effect). Also dramatically increase your supply coupling from the 100n
as I thought you mentioned using in one of you other post. Your
driving more capacitance than that, so how can that amount of supply
capacitance hold charge ! As I said make sure you read up on all the
app notes as they go into all this detail.
best of luck
Go Back To The Cyber-Spy.Com
Usenet Web Archive Index Of
The sci.electronics.design Newsgroup