From: email@example.com (Winfield Hill)
Subject: Re: zero-power toggle circuit; was, how to master electronics
Date: 18 Nov 2002 15:59:48 -0800
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NNTP-Posting-Date: 18 Nov 2002 23:59:48 GMT
Fred Bloggs wrote ...
> Terry Pinnell wrote:
>> By bad luck my initial choice of MOSFET wouldn't toggle at all.
>> But subsequent tests with a variety of types gave surprisingly
>> inconsistent results. I've shown my test circuit and results at
>> Given that my simulation of Win's earlier circuit (using a similar
>> button-pressing section) seemed 'robust', I'm puzzled why these are
>> relatively erratic. Is it a flaw in my circuit or interpretation?
>> Or is the circuit itself genuinely sensitive?
> Anyone can see that the circuit has inherently defective time constant
> allocation. The problem arises from the fact that at turn-off the
> 2N7000 gate circuit time constant is at most a factor of approximately
> 10 greater than the p_channel gate time constant. Turn-on is a done deal
> because the p-channel gate capacitance is charged through the ultra-low
> Rds of the 2N7000, but at turn-off, this capacitance must discharge
> through the 100k R4, and this is happening at the same time as the
> 2N7000 gate is re-charging through R2 because the output node still has
> voltage on it. If the thresholds of both mosfets are low then you have
> the situation where the 2N7000 requires only a small fraction of the
> gate circuit time-constant to turn back on, and the p-channel requires
> an integer multiple of its gate circuit time constant to start turning
> off. This is the root cause of failure to toggle off, the 2N7000 turns
> back-on before the p-channel can turn-off enough- very bad circuit- and
> SPICE is not required. Reduce R4 to 10K or increase C1 to 1U for added
> turn-off margin.
I'm sorry, but I'm not persuaded by the above reasoning.
I've re-added the schematic below for discussion clarity. (At least I
think this is the circuit Terry was simulating. It's not fully Wafer's
circuit because I took the liberty of eliminating a 10k resistor from
Q1's drain to Q2's gate, and Wafer's diode at the output. Hmm, maybe
that's why Wafer isn't here defending his circuit?)
: ,--------+----(O) V+
: | | 6 to 9V
: R4 |
: 100k |
: | |
: +----||--+ Q2
: x | ||>-' BSS138
: ,-----------------------+ |--, BSS110
: | R2 | |
: R1 ,-- 220k --- | -------+--+---(o)
: 1M5 S1 | | | |
: | _|_ | |--' _|_ |
: +---o o----+ ||<-, Q1 /_\ LOAD
: | +--------||--+ 2N7002 | |
: | 0.1uF | | 2N7000 | |
: === C1 R3 '--------+--+---(O)
: | 100k |
: gnd | gnd
The complaint is about time constants for Q2's turnoff, right? We'll
see that for Wafer's 9V battery, this isn't an issue. OK, press S1 for
the shortest humanly-possible time, say 5ms. (Any switch bounce is OK,
because we're only concerned with the total switch-activation time.)
What happens during this 5ms? We start with point x at 0V, so C1 also
has 0 volts. After the button press, C1 still has 0V, or certainly no
more than 10mV from discharging Q1's gate capacitance (which takes no
more than 50ns). How fast will Q1's drain = Q2's gate charge to within
1.0V of the V+ rail, so Q2 can turn off? With the button pressed and
C1 discharged, point x rises toward 94% of V+ with a 10 to 20us time
constant, so it rapidly goes toward R4/(R1+R4) = 6% of V+ rail. Wafer
specified his circuit for use with 9V batteries, or a 6 to 10V range.
That's 600mV max on Q2's gate, and we can be confidant 0.6V shouldn't
be able to hold it on. How many time constants do we need? Let's
be conservative and say ten time constants of the R-C time involved.
That's under 200us, which is still well under our 5ms switch limit.
What about Q2's drain? We've got a short, under 30us, time constant
there as well, so 5t is under 150us. What about Q1's gate? That's
been discharged and is held down by C1.
We're already 350us into the process, what's happening to C1? Should
we worry about the 22ms C1 charging time constant through R2? Given
our conservative 220us calculations above, this seems not an issue.
It doesn't appear Q1 can turn back on before the 350us is up...
So I think the circuit should work just as Wafer has asserted.
However, a lower R4 resistor value, like 22k, is harmless enough, and
would provide a safety margin for use at higher voltages, like 18V,
by changing the R4/(R1+R4) ratio from 6% to a safer 2%.