From: Terry Pinnell
Subject: Re: zero-power toggle circuit; was, how to master electronics
Date: Tue, 19 Nov 2002 20:40:40 +0000
References: <3DD39D90.firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org>
NNTP-Posting-Date: Tue, 19 Nov 2002 20:40:56 +0000 (UTC)
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Tony Williams wrote:
>In article <email@example.com>,
> Terry Pinnell wrote:
>> That seems to square with my results, Tony,
>> It also looks to me as if the failures are, as you suggest, associated
>> with higher powered MOSFETS, which have higher drain-gate capacitance.
> If you have the time Terry, repeat the
> simulations with a probe across R3, ie
> look at the gate-source voltage of Q1.
That was included in
(waveform at 'FET gate')
> The voltage there should only exceed 0.8V
> when it is supposed to... the On-going
> closure of S1 and when it is latched On.
> Look carefully at it when S1 is closed to
> turn Off... see if it drops to 0v, then
> immediately ramps up to >0.8V.
Here's a similar analysis for one of the few MOSFETs that works OK.
Thanks for the warning about the long time constant. Minimum gap
before was about 700 mS, but increasing it to about 1.2 S made no
difference to success/failure. Note that in the later analysis I've
increased the gaps.
Hobbyist, West Sussex, UK