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From: Terry Pinnell
Subject: Re: zero-power toggle circuit; was, how to master electronics
Date: Wed, 20 Nov 2002 15:42:59 +0000
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NNTP-Posting-Date: Wed, 20 Nov 2002 15:43:15 +0000 (UTC)
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Terry Pinnell wrote:
>Winfield Hill wrote:
>> Wafer's circuit uses rather high resistor values, much higher than
>> mine. This shouldn't be completely necessary for a circuit that's
>> off when it matters. If it turns on and powers a 10mA load, what's
>> the harm in another 0.5mA for the switching circuit? It seems to
>> work well enough for Wafer, but halving the R values for small FETs
>> would make me more comfortable, and further reducing the resistances
>> in proportion to any increased FET capacitances would also be wise.
>> Why don't you try that in your model?
>OK, will do.
I spent more time, but didn't get much further with several of the
MOSFET types. Then I discovered the main cause. I received a message
from a professional CM user, Ron Berthiaume, who subscribes to a CM
mailing list I use. Turns out CM has screwed up some of the MOSFET
classifications, and as luck would have it, IRF9513 was one of them.
I'm not confident of summarising it accurately, so I've pasted most of
Ron's analysis here:
1) The IRF9513 FET doesn't work in circuit. (Circuitmaker Problem) I
can't find an IRF9513 datasheet but, based on simulation, the device
appears to be a depletion mode FET not an enhancement mode FET. A
depletion mode FET is on without any gate voltage and a reverse
polarity (+V for a PFET, -V for a NFET) needs to be applied to turn
it off. The subject circuit requires the FET to be off with zero gate
voltage so a depletion FET won't work for this application. This
device shouldn't be in the Circuitmaker enhancement FET list. A
RFF60P06 which is a depletion mode FET is also on the list so be
careful in picking a FET at random.
2) Some FETs work and some don't. (Circuit Problem) This is due to the
high value of the 100K resistor (R4) connected between the gate and
source of the upper FET(Q2) , inconjunction with the characteristics
of the FET selected.
- Gate Threshold Voltage of Upper FET Lets start with a condition
where the output voltage is on (High). To turn the output voltage,
off Q2 needs to turn off. This is initiated by the push button switch
connecting the discharged cap (C1) to the gate of Q1 to turn it off.
When Q1 opens, R4 will attempt to pull the gate of Q2 to the it's
source voltage to turn it off. At this instant the cap voltage is 0V
and the cap starts to charge through both R4 (100K) and R1 (1.5 Meg).
The current at this time will be 10V/1.6Meg or 6.25 uA. The voltage
across R4 will be 0.625V and may be greater than the gate threshold
voltage (Vgth) of Q2 not allowing it to turn off.
- Race Condition Between C1 Charging and Q2 Gate Discharging When the
output is toggled from a high to a low state, C1 is at 0V and when
the switch is closed the gate of Q1 is pulled low turning it off and
its drain becomes a high impedance. C1 will start to charge through
both R1 and (through the switch) R2 (which is connected to the
output which is high at this point). With Q1 off, R4 will start to
pull up the gate of Q2 to turn it off. Now R4 is 100K and can't
discharge the gate instantly due to the Gate capacitance of Q2 (Cgs
and Cgd), the drain capacitance of Q1, plus the reverse capacitance
of D1. Of these capacitances the gate capacitance of Q2 should be
predominant, especially with high power FETS whose Cgs can be
effectively as high as 0.01uF due to large die size and the miller
effect. Additionally the gate voltage started at ground and has to
charge all the way up to V+(10V) - Vgth before the upper FET turns
off. This is the turn off delay (Toff) of Q2 and can be a fairly long
time especially with low RDSon FETS (large gates).
Note that during the turn-off delay of Q2 the output remains high and
C1 will charge fairly quickly through R2 (220K). Now if Q2 turns off
before C1 charges to the Vgth of Q1, the output switches low (as
intended) and R4 will start to discharges C1, keeping Q1 off. At this
point the output has toggled properly. When the momentary switch
finally opens C1 will charge up through R1 to get ready for the next
A failure arises however if C1 charges up to the Vgth of Q1 before Q2
turns off (due to its of turn-off delay). If C1 reaches Vgth, Q1 will
turn back on and, since its RDSon is only a few ohms, will quickly
pull the gate of Q2 back to ground. This keeps Q2 turned on and the
output voltage will stay high. As long as the switch is closed C1
will continue to charge through R2, keeping Q1 and Q2 on, and the
output won't toggle low. When the momentary switch opens, C1 is
disconnected from the gate of Q1 and will discharge to ground through
R1 and Q1drain to get ready for the next trigger.
You can also aggravate the failure mechanism by increasing R4,
decreasing R2, or decreasing C1.
Sr. Applications Manager
Fairchild Semiconductor, Power Management Group
Hobbyist, West Sussex, UK
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