The Cyber-Spy.Com Usenet Archive Feeds Directly From The Open And Publicly Available Newsgroup Sci.Electronics.Design
This Group And Thousands Of Others Are Available On Most IS NNTP News Servers On Port 119.
Cyber-Spy.Com Is NOT Responsible For Any Topic, Opinions Or Content Posted To This Or Any Other Newsgroup. This Web Archive Of The Newsgroup And Posts Are For Informational Purposes Only.
From: Tony Williams
Newsgroups: sci.electronics.design
Subject: Re: zero-power toggle circuit; was, how to master electronics
Date: Thu, 21 Nov 2002 10:44:41 +0000 (GMT)
Organization: None
Message-ID: <4b98d1b7f4tonyw@ledelec.demon.co.uk>
References: <3DD39D90.3020001@hotpop.com> <66hftu8n61qr8h2u6dg0qo9blpgqet859s@4ax.com> <4b97cac3a2tonyw@ledelec.demon.co.uk> <0riktuo44a75tn450bdm13uh8096hko81q@4ax.com> <4b97e4b30btonyw@ledelec.demon.co.uk> <4b986e5dc9tonyw@ledelec.demon.co.uk>
NNTP-Posting-Host: ledelec.demon.co.uk
NNTP-Posting-Date: Thu, 21 Nov 2002 10:45:20 +0000 (UTC)
User-Agent: Pluto/1.14i (RISC-OS/3.60)
In article ,
Winfield Hill wrote:
> Rf 33k ,----------------+----(O)
> ,---------/\/\/\------- | --, |
> | Rf< | | \ | \ | 100 ||--+ p-channel
> +----| O ----+------| O --+--/\/\--||->' "as big as
> | | / | | / |--, one wants"
> | CD4069 \ 1.0M | |
> | / Rs gnd '----(O)
> | _|_ | to LOAD
> '-----o o-----+ SIMPLE INVERTER TOGGLE
> | C
> --- 0.1uF
> --- SW NOT GND'D
> | Rs C >> SW BOUNCE
> gnd
The advantage of the npn/pnp bistable was that it is
automatically off at power-up (Terry's probs excepted).
But if CMOS is acceptable, an interesting "npn/pnp"
bistable can be realised in just one gate of a 4066.
The other gates can be used to do the twiddly bits
around the bistable. The other interesting thing
about CMOS (v MOSFETs) is that the switching thresholds
are better defined, in fact nicely proportional to Vcc.
TG= 4066 Transmission Gate |Vcc
+----------------------+-----+-->P-Fet
| | | Drain
| 100pF? * \
| + 0v--||----+----TG1>/ /10k
P/B->| | * \
| + | 1meg | |
| ,---------/\/\--------+-->P-Fet
| | | 220k | | Gate
| | +--/\/\--+ |
| | * | *
+-/\/\----TG2>/ +-TG3>/
| | * | *
\ +------+ \ |
10k/ | 10k/ |
\ C1===0.1u \ |
| | | |
+------+---------------+-----+-->0v
TG1 (and the 220k) is the 1-gate bistable.
TG2 connects C1 when the P/B is pressed.
TG3 is the output inverter, driving the P-FET,
and providing the charging volts for C1.
TG4 is spare... could be used (in conjunction with
a sense-R and pnp Tr) as an overload controller.
Several possibilities available.
a) Simple current-limit, no unlatch.
(PNP shorting the P-FET drive volts.)
b) Force an unlatch for a current overload.
(TG4 between TG1 gate and 0v.)
c) Unlatch only if there is an overcurrent AND
the P-Fet drain is pulled far away from Vcc.
(TG4 between TG1 gate and P-FET drain.)
d) Any of the above, but with a simple RC delay
to allow for load switch-on surge.
--
Tony Williams.
Go Back To The Cyber-Spy.Com Usenet Web Archive Index Of The sci.electronics.design Newsgroup
|